EP1C3T100C6 | |
|---|---|
| Manufacturer Part Number | EP1C3T100C6 |
| Description | IC CYCLONE FPGA 2910 LE 100-TQFP |
| Manufacturer | Altera |
| Series | Cyclone® |
| EP1C3T100C6 datasheets |
|
Availability: In stock
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Specifications of EP1C3T100C6 | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 2910 | Number Of Labs/clbs | 291 |
| Total Ram Bits | 59904 | Number Of I /o | 65 |
| Voltage - Supply | 1.425 V ~ 1.575 V | Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 85°C | Package / Case | 100-TQFP, 100-VQFP |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Number Of Gates | - |
| Other names | 544-1014 | ||
PrevNext
Cyclone Device Handbook, Volume 1
performance and flexibility. Each LE can drive 30 other LEs through fast
local and direct link interconnects.
connection.
Figure 2–3. Direct Link Connection
Direct link interconnect from
left LAB, M4K memory
block, PLL, or IOE output
Direct link
interconnect
to left
Interconnect
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include two clocks, two clock enables, two
asynchronous clears, synchronous clear, asynchronous preset/load,
synchronous load, and add/subtract control signals. This gives a
maximum of 10 control signals at a time. Although synchronous load and
clear signals are generally used when implementing counters, they can
also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB's
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1 signal will also use labclkena1. If
the LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. Deasserting the clock enable signal will turn off
the LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. The asynchronous load acts as a preset when the
asynchronous load data input is tied high.
2–4
Preliminary
Local
Figure 2–3
shows the direct link
Direct link interconnect from
right LAB, M4K memory
block, PLL, or IOE output
Direct link
interconnect
to right
LAB
Altera Corporation
May 2008
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