IC CYCLONE FPGA 2910 LE 100-TQFP

 

EP1C3T100C6

Manufacturer Part NumberEP1C3T100C6
DescriptionIC CYCLONE FPGA 2910 LE 100-TQFP
ManufacturerAltera
SeriesCyclone®
EP1C3T100C6 datasheets

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Specifications of EP1C3T100C6

Number Of Logic Elements/cells2910Number Of Labs/clbs291
Total Ram Bits59904Number Of I /o65
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case100-TQFP, 100-VQFP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Gates-
Other names544-1014  
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Page 12/106

Download datasheet (2Mb)Embed
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Cyclone Device Handbook, Volume 1
Figure 2–5. Cyclone LE
LAB Carry-In
Carry-In1
addnsub
Carry-In0
data1
data2
Look-Up
data3
Table
(LUT)
data4
labclr1
labclr2
Asynchronous
labpre/aload
Clear/Preset/
Load Logic
Chip-Wide
Reset
Clock &
Clock Enable
Select
labclk1
labclk2
labclkena1
labclkena2
Each LE's programmable register can be configured for D, T, JK, or SR
operation. Each register has data, true asynchronous load data, clock,
clock enable, clear, and asynchronous load/preset inputs. Global signals,
general-purpose I/O pins, or any internal logic can drive the register's
clock and clear control signals. Either general-purpose I/O pins or
internal logic can drive the clock enable, preset, asynchronous load, and
asynchronous data. The asynchronous load data input comes from the
data3 input of the LE. For combinatorial functions, the LUT output
bypasses the register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources. This
allows the LUT to drive one output while the register drives another
output. This feature, called register packing, improves device utilization
because the device can use the register and the LUT for unrelated
2–6
Preliminary
Register chain
routing from
previous LE
LAB-wide
Register Bypass
Synchronous
Load
LAB-wide
Synchronous
Clear
Synchronous
Carry
Load and
Chain
Clear Logic
Carry-Out0
Carry-Out1
LAB Carry-Out
Programmable
Packed
Register
Register Select
LUT chain
routing to next LE
Row, column,
PRN/ALD
and direct link
D
Q
routing
ADATA
ENA
CLRN
Row, column,
and direct link
routing
Local Routing
Register chain
Register
output
Feedback
Altera Corporation
May 2008

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