EP1AGX90EF1152I6N Altera, EP1AGX90EF1152I6N Datasheet
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EP1AGX90EF1152I6N Summary of contents
Page 1
... Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © December 2009 Altera Corporation Section I. Arria GX Device Data Sheet Arria GX Device Handbook, Volume 1 GX ® ...
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... I–2 Arria GX Device Handbook, Volume 1 Section I: Arria GX Device Data Sheet © December 2009 Altera Corporation ...
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... Phase compensation FIFO buffer performs clock domain translation between ■ the transceiver block and the logic array Channel aligner compliant with XAUI ■ © December 2009 Altera Corporation 1. Arria GX Device Family Overview ® family. The Arria GX FPGA Arria GX Device Handbook, Volume 1 ...
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... Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1 Support for high-speed external memory including DDR and DDR2 SDRAM, ■ and SDR SDRAM Support for multiple intellectual property megafunctions from Altera ■ MegaCore Support for remote configuration updates ■ Table 1–1 lists Arria GX device features for FineLine BGA (FBGA) with flip chip packages ...
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... I/O pins are migratable. Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part Source-Synchronous Channels Transceiver Device Channels Receive EP1AGX20C 4 EP1AGX35C 4 EP1AGX50C 4 EP1AGX60C 4 EP1AGX35D 8 EP1AGX50D 8 © December 2009 Altera Corporation EP1AGX50C 29, 42 197 313 140 242 1 2 2,475,072 56 104 14 26 ...
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... Chapter 1: Arria GX Device Family Overview Document Revision History Maximum User I/O Pin Count 1152-Pin 780-Pin FBGA FBGA (29 mm) (35 mm) 350 — — 514 — 538 1152 Pins 1.00 1225 35 × 35 Summary of Changes — — — — © December 2009 Altera Corporation ...
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... Arria GX family. Table 2–1. Arria GX Transceiver Channels Device EP1AGX20C EP1AGX35C EP1AGX35D EP1AGX50C EP1AGX50D EP1AGX60C EP1AGX60D EP1AGX60E EP1AGX90E © December 2009 Altera Corporation 2. Arria GX Architecture ® device family. Arria GX transceivers are Number of Transceiver Channels ...
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... Matcher Byte Decoder XAUI Deserializer Lane Deskew Byte 8B/10B Serializer Encoder Chapter 2: Arria GX Architecture Transceivers RX1 TX1 RX0 TX0 REFCLK_1 REFCLK_0 RX2 TX2 RX3 TX3 FPGA Fabric m Phase Compensation FIFO Buffer (2) m Phase Compensation FIFO Buffer (2) © December 2009 Altera Corporation ...
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... The CMU is further divided into three sub-blocks: One transmitter PLL ■ ■ One central clock divider block ■ Four local clock divider blocks (one per channel) © December 2009 Altera Corporation ® II MegaWizard ™ Plug-in Manager for Arria GX Device Handbook, Volume 1 2–3 ...
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... Charge Frequency Pump + Loop down Detector INCLK Filter Chapter 2: Arria GX Architecture Transceivers Transmitter High-Speed Serial and Low-Speed Parallel Clocks Transmitter High-Speed Serial and Low-Speed Parallel Clocks Transmitter PLL Voltage High Speed (1) /L Controlled Serial Clock Oscillator © December 2009 Altera Corporation ...
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... PCS logic. The byte serializer is bypassed in GIGE mode. After serialization, the byte serializer transmits the least significant byte (LSByte) first and the most significant byte (MSByte) last. © December 2009 Altera Corporation Specifications 50 MHz to 622.08 MHz 600 Mbps to 3.125 Gbps ...
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... K28.5 code groups for synchronizing before it starts encoding the input data or control character. Arria GX Device Handbook, Volume 1 (Note {8'h02,8'h03 LSByte MSByte 8'h01 8'h00 xxxxxxxxxx chapter 8B-10B Conversion MSB Chapter 2: Arria GX Architecture Transceivers D3 xxxx D2 D2 LSByte MSByte 8'h03 8'h02 Specifications Ctrl LSB © December 2009 Altera Corporation ...
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... The serializer feeds the data LSB to MSB to the transmitter output buffer. © December 2009 Altera Corporation lists the code conversion. PCS Code-Group Dxx ...
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... Arria GX Device Handbook, Volume From 8B/10B D4 Encoder Low-speed parallel clock CMU Central / High-speed serial clock Divider chapter. Figure 2–8, is directly driven by the high-speed data Chapter 2: Arria GX Architecture Transceivers Transmitter D0 Output Buffer ) of the output driver may be CM Arria GX © December 2009 Altera Corporation ...
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... The common mode voltage is the average of V Figure 2–9. Differential Signaling Single-Ended Waveform True Complement Differential Waveform (Differential − high low © December 2009 Altera Corporation Programmable Pre-Emphasis ) can be statically set by using the OD Figure 2–9. The differential amplitude – single-ended HIGH LOW HIGH V high ...
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... Arria GX Device Handbook, Volume 1 2–10. Pre-emphasis is set statically using the ALTGXB megafunction MAX MIN V MAX − 1) × 100 Pre-Emphasis % = ( V MIN /V MAX MIN Chapter 2: Arria GX Architecture Transceivers – 1) × 100, where V is the the differential MIN © December 2009 Altera Corporation ...
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... Impedance mismatch boundaries can also cause signal degradation. Equalization in the receiver diminishes the lossy attenuation effects of the PCB at high frequencies. © December 2009 Altera Corporation Figure 2–11. You can disable the receiver’s internal termination 100-Ω ...
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... PLL to lock to data). Arria GX Device Handbook, Volume 1 /M rx_pll_locked PFD up dn rx_cruclk CP Clock Recovery Unit ( CRU ) Control Chapter 2: Arria GX Architecture Transceivers VCO /L rx_freqlocked High-speed serial recovered clk Low-speed parallel recovered clk © December 2009 Altera Corporation ...
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... The serial data is assumed to be received with LSB first, followed by MSB. It feeds the deserialized 8- or 10-bit data to the word aligner, as shown in © December 2009 Altera Corporation ) operates at half rate. CO chapter. ...
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... Arria GX Device Handbook, Volume Chapter 2: Arria GX Architecture Transceivers To Word Aligner © December 2009 Altera Corporation ...
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... The running disparity error rx_disperr and running disparity value rx_runningdisp are sent along with aligned data from the 8B/10B decoder to the FPGA. You can ignore or act on the reported running disparity value and running disparity error signals. © December 2009 Altera Corporation datain dataout Word ...
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... The reception of four consecutive misaligned /A/ code groups restarts the channel alignment sequence and sends the rx_channelaligned signal low. Arria GX Device Handbook, Volume 1 Chapter 2: Arria GX Architecture Transceivers © December 2009 Altera Corporation ...
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... Table 2–5 lists the maximum frequency difference that the rate matcher can tolerate in XAUI, PCI Express (PIPE), GIGE, and Basic functional modes. Table 2–5. Rate Matcher PPM Tolerance Function Mode PCI Express (PIPE) © December 2009 Altera Corporation ...
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... For insertion, the rate matcher inserts skip characters such that the number of skip characters at the output of rate matcher does not exceed five. Arria GX Device Handbook, Volume 1 Chapter 2: Arria GX Architecture Transceivers © December 2009 Altera Corporation ...
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... The receiver state machine operates in Basic, GIGE, PCI Express (PIPE), and XAUI modes. In GIGE mode, the receiver state machine replaces invalid code groups with K30.7. In XAUI mode, the receiver state machine translates the XAUI PCS code group to the XAUI XGMII code group. © December 2009 Altera Corporation ...
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... Transmitter PCS Byte 8B/10B Serializer Encoder Receiver PCS Byte Rate 8B/10B De- Match Decoder Serializer FIFO Chapter 2: Arria GX Architecture Transceivers Arria GX Transceiver Arria GX Transceiver Transmitter PMA Serializer Serial Loopback Receiver PMA Clock De- Word Recovery Serializer Aligner Unit © December 2009 Altera Corporation ...
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... Serializer 20 FIFO FPGA Logic Array BIST Incremental Verify RX Phase Compen- sation FIFO Receiver Digital Logic © December 2009 Altera Corporation 2–18, the serial data output from the transmitter serializer is looped BIST PRBS Generator 8B/10B Encoder Byte Rate 8B/10B De- Match Decoder serializer FIFO 2– ...
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... Chapter 2: Arria GX Architecture Transceivers setting level. OD Analog Receiver and Transmitter Logic Serializer Reverse Serial Pre-CDR Loopback BIST PRBS Verify Clock De- Deskew Word Recovery serializer FIFO Aligner Unit Transmitter PMA Serializer Receiver PMA Clock De- Word Recovery Serializer Aligner Unit © December 2009 Altera Corporation ...
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... The following two powerdown signals are available per transceiver block and can be used to shut down an entire transceiver block that is not being used: ■ gxb_powerdown ■ gxb_enable © December 2009 Altera Corporation 2–21, the serial data received on the rx_datain port in reverse 2–23 Arria GX Device Handbook, Volume 1 ...
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... Chapter 2: Arria GX Architecture Transceivers — — v — — — — — — — — — — — — — — — © December 2009 Altera Corporation — v — ...
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... PLL. Figure 2–22. Input Reference Clock Sources Inter-Transceiver Lines [2] Inter-Transceiver Lines [1] Inter-Transceiver Lines [0] Dedicated REFCLK0 Dedicated REFCLK1 Inter-Transceiver Lines [2:0] © December 2009 Altera Corporation /2 /2 Global Clock (1) Global Clock (1) 2–25 Transceiver Block 2 Transceiver Block 1 Transceiver Block 0 Transmitter PLL ...
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... Figure 2–23. Global Clock Resources in Arria GX Devices CLK[3..0] Arria GX Device Handbook, Volume 1 chapter. Figure 2–24 show the available GCLK and RCLK resources in Arria CLK[15..12 GCLK[15..12] 1 GCLK[3..0] 2 GCLK[4.. CLK[7..4] Chapter 2: Arria GX Architecture Transceivers Arria GX Transceiver Block GCLK[11..8] Arria GX Transceiver Block © December 2009 Altera Corporation ...
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... Region1 8 LRIO clock Table 2–8. Available Clocking Connections for Transceivers in EP1AGX60E and EP1AGX90E Source Global Clock v Region0 8 LRIO clock v Region1 8 LRIO clock v Region2 8 LRIO clock v Region3 8 LRIO clock © December 2009 Altera Corporation CLK[15..12 RCLK RCLK [31..28] [27..24] RCLK [3.. RCLK [7..4] ...
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... EP1AGX90 478 Arria GX Device Handbook, Volume 1 Table 2–9 shows the Arria GX LAB structure. M4K RAM M-RAM Blocks Columns/Blocks 118 1 140 1 242 2 252 2 400 4 Chapter 2: Arria GX Architecture Logic Array Blocks lists Arria GX device DSP Block Columns/Blocks © December 2009 Altera Corporation ...
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... LAB through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each ALM can drive 24 ALMs through fast local and direct link interconnects. © December 2009 Altera Corporation Row Interconnects of Variable Speed & Length LAB Local Interconnect is Driven from Either Side by Columns & ...
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... LAB 2–27. Each LAB’s clock and clock enable signals are linked. For Chapter 2: Arria GX Architecture Logic Array Blocks Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect to right © December 2009 Altera Corporation ...
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... Arria GX ALM while the connections in the ALM. © December 2009 Altera Corporation There are two unique clock signals per LAB. labclk0 ...
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... Arria GX Device Handbook, Volume 1 carry_in shared_arith_in reg_chain_in adder0 adder1 carry_out shared_arith_out reg_chain_out Chapter 2: Arria GX Architecture Adaptive Logic Modules To general or local routing To general local routing reg0 To general local routing reg1 To general or local routing © December 2009 Altera Corporation ...
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... Chapter 2: Arria GX Architecture Adaptive Logic Modules Figure 2–29. Arria GX ALM Details © December 2009 Altera Corporation 2–33 Arria GX Device Handbook, Volume 1 ...
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... ALM operating mode to use for optimal performance. Arria GX Device Handbook, Volume 1 Figure 2–29). For each set of output drivers, two ALM outputs Figure 2–28)the eight data inputs from the LAB local interconnect; 2–30. Chapter 2: Arria GX Architecture Adaptive Logic Modules “LAB © December 2009 Altera Corporation ...
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... Normal mode provides complete backward compatibility with four-input LUT architectures. Two independent functions of four inputs or less can be implemented in one Arria GX ALM. In addition, a five-input function and an independent three-input function can be implemented without sharing inputs. © December 2009 Altera Corporation dataf0 datae0 5-Input ...
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... The shared inputs are dataa, Implementation in 1 ALM dataf0 datae0 Six-Input dataa out0 LUT datab (Function0) datac datad out1 Six-Input LUT (Function1) datae1 dataf1 Figure 2–32). If datae1 and dataf1 are used, the Chapter 2: Arria GX Architecture Adaptive Logic Modules combout0 combout1 © December 2009 Altera Corporation ...
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... Note to Figure 2–33: (1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available. © December 2009 Altera Corporation Note (1), (2) 6-Input LUT These inputs are available for register packing. ...
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... LUT D Q reg0 4-Input LUT adder1 4-Input LUT D Q 4-Input reg1 LUT carry_out < Chapter 2: Arria GX Architecture Adaptive Logic Modules To general or local routing To general or local routing To general or local routing To general or local routing © December 2009 Altera Corporation ...
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... To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB before connecting to the next LAB. © December 2009 Altera Corporation Adder output is not used. ...
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... LUT D Q reg0 4-Input LUT 4-Input LUT D Q 4-Input reg1 LUT carry_out shared_arith_out Chapter 2: Arria GX Architecture Adaptive Logic Modules “MultiTrack Interconnect” To general or local routing To general or local routing To general or local routing To general or local routing © December 2009 Altera Corporation ...
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... For enhanced fitting, a long shared arithmetic chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column. Similar to carry chains, shared arithmetic © December 2009 Altera Corporation ALM Implementation ALM 1 ...
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... For more information about register chain interconnect, refer to “MultiTrack Interconnect” on page Arria GX Device Handbook, Volume 1 2–44. Figure 2–38). The Quartus II Compiler 2–44. Chapter 2: Arria GX Architecture Adaptive Logic Modules “MultiTrack © December 2009 Altera Corporation ...
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... NOT gate push-back technique. Arria GX devices support simultaneous asynchronous load/preset and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one load/preset signal. © December 2009 Altera Corporation (Note 1) From Previous ALM Within The LAB ...
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... R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 and C16 interconnects for connections from one row to another. Additionally, R4 interconnects can drive R24 interconnects. Arria GX Device Handbook, Volume 1 Chapter 2: Arria GX Architecture MultiTrack Interconnect Figure 2–39 © December 2009 Altera Corporation ...
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... ALM in the LAB for fast shift registers. These ALM-to-ALM connections bypass the local interconnect. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. chain interconnects. © December 2009 Altera Corporation (Note 1), (2), (3) Adjacent LAB can ...
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... Arria GX Device Handbook, Volume 1 Local Interconnect Routing Among ALMs in the LAB ALM 1 Register Chain Routing to Adjacent ALM's Register Input ALM 2 Local ALM 3 Interconnect ALM 4 ALM 5 ALM 6 ALM 7 ALM 8 Chapter 2: Arria GX Architecture MultiTrack Interconnect © December 2009 Altera Corporation ...
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... These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[5..0]. © December 2009 Altera Corporation (Note 1) Local Interconnect 2– ...
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... M-RAM Block (4K × 144 Bits) 380 MHz 290 MHz — © December 2009 Altera Corporation ...
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... RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes: Simple dual-port RAM ■ ■ Single-port RAM ■ FIFO ■ ROM Shift register ■ © December 2009 Altera Corporation M512 RAM Block M4K RAM Block (32 × 18 Bits) (128 × 36 Bits — v ...
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... M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. array interface. Arria GX Device Handbook, Volume 1 6 outclocken inclocken inclock outclock Figure 2–43 shows the M512 RAM block to logic Chapter 2: Arria GX Architecture TriMatrix Memory Figure 2–42 wren outclr rden © December 2009 Altera Corporation ...
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... The six labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. ALMs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in © December 2009 Altera Corporation 36 dataout M4K RAM ...
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... LAB. M4K RAM block outputs can also connect to left and right LABs through direct link interconnect. to logic array interface. Arria GX Device Handbook, Volume 1 6 clocken_b clock_b renwe_a clock_a clocken_a Figure 2–45 Chapter 2: Arria GX Architecture TriMatrix Memory renwe_b aclr_b aclr_a shows the M4K RAM block © December 2009 Altera Corporation ...
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... The six labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. ALMs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in © December 2009 Altera Corporation 36 dataout M4K RAM ...
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... Figure 2–49 show the interface between the M-RAM block and the Chapter 2: Arria GX Architecture TriMatrix Memory Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect clock_b Local Interconnect Figure 2–47 shows an example © December 2009 Altera Corporation ...
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... Block M-RAM Block M4K M512 Blocks Blocks Note to Figure 2–47: (1) The device shown is an EP1AGX90 device. The number and position of M-RAM blocks vary in other devices. © December 2009 Altera Corporation (Note 1) M-RAM Block M-RAM Block DSP LABs DSP Blocks Blocks Arria GX Device Handbook, Volume 1 ...
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... Only R24 and C16 interconnects cross the M-RAM block boundaries. Arria GX Device Handbook, Volume 1 (Note 1) Row Unit Interface Allows LAB Rows to Drive Port B Datain, Dataout, Address and Control Signals to and from M-RAM Block M-RAM Block Port B Chapter 2: Arria GX Architecture TriMatrix Memory LABs in Row M-RAM Boundary © December 2009 Altera Corporation ...
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... L5 and R0 to R5). Table 2–12. M-RAM Row Interface Unit Signals (Part Unit Interface Block © December 2009 Altera Corporation C4 Interconnect R4 and R24 Interconnects Row Interface Block M-RAM Block to ...
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... TriMatrix Embedded chapter. © December 2009 Altera Corporation Digital Signal Processing Block Output Signals ...
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... ALMs easier, saves ALM routing resources, and increases performance because all connections and blocks are in the DSP block. © December 2009 Altera Corporation DSP Block Column DSP Block ...
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... DSP block configured for 18 × 18-bit multiplier mode. Arria GX Device Handbook, Volume 1 (Note 1) Total 9 × 9 DSP Blocks Multipliers 112 26 208 32 256 44 352 Chapter 2: Arria GX Architecture Digital Signal Processing Block Total 18 × 18 Total 36 × 36 Multipliers Multipliers 104 26 128 32 176 44 © December 2009 Altera Corporation ...
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... CLRN D Q ENA CLRN D Q ENA CLRN Optional Serial Shift Register Outputs to Next DSP Block the Column ENA CLRN © December 2009 Altera Corporation Multiplier Stage Optional Stage Configurable as Accumulator or Dynamic Adder/Subtractor D Q ENA CLRN Adder/ Adder/ Subtractor/ Subtractor/ Accumulator Accumulator ...
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... Four multipliers with four product outputs Two 52-bit — multiply-accumulate blocks Two two-multiplier adder (one 18 × 18 complex multiply) One four-multiplier adder Chapter 2: Arria GX Architecture Digital Signal Processing Block 36 × 36 One multiplier with one product output — — — © December 2009 Altera Corporation ...
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... Chapter 2: Arria GX Architecture Digital Signal Processing Block Figure 2–52 and Figure 2–52. DSP Block Interconnect Interface © December 2009 Altera Corporation Figure 2–53 show the DSP block interfaces to LAB rows. DSP Block OA[17..0] R4, C4 & Direct OB[17..0] Link Interconnects A1[17..0] B1[17..0] OC[17 ...
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... Row Structure 16 12 Control 36 A[17..0] OA[17..0] B[17..0] OB[17..0] Row Interface Block 36 Inputs per Row 36 Outputs per Row Chapter 2: Arria GX Architecture Digital Signal Processing Block Direct Link Interconnect from Adjacent LAB LAB 36 Table 2–15. DSP Blocks in Arria GX Devices © December 2009 Altera Corporation ...
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... December 2009 Altera Corporation Data Inputs Data Outputs A1[17..0] OA[17..0] B1[17..0] OB[17..0] A2[17..0] OC[17..0] B2[17..0] OD[17..0] A3[17..0] OE[17..0] B3[17..0] OF[17..0] A4[17..0] OG[17..0] B4[17..0] OH[17..0] Arria GX Device Handbook, Volume 1 2– ...
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... Global Clocks 16 16 Clock pins, PLL outputs, core routings, inter-transceiver clocks v v Figure 2–54 shows the 12 dedicated CLK pins driving global Chapter 2: Arria GX Architecture PLLs and Clock Networks 2–55. Internal logic and enhanced Regional Clocks 32 8 — v © December 2009 Altera Corporation ...
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... PLL outputs internal logic. The regional clock networks provide the lowest clock delay and skew for logic contained in a single quadrant. The CLK pins symmetrically drive the RCLK networks in a particular quadrant, as shown in Figure 2–55. © December 2009 Altera Corporation CLK[15..12] Global Clock [15..0] Global Clock [15..0] CLK[7..4] 2– ...
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... RCLK RCLK [31..28] [27..24] RCLK RCLK [3..0] [23..20] RCLK RCLK [7..4] [19..16] RCLK RCLK [11..8] [15..12 CLK[7..4] Figure 2–56. Corner PLLs cannot drive Chapter 2: Arria GX Architecture PLLs and Clock Networks Arria GX Transceiver Block Arria GX Transceiver Block © December 2009 Altera Corporation ...
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... You can use the Quartus II software to control whether a clock input pin drives either a GCLK, RCLK, or dual-RCLK network. The Quartus II software automatically selects the clocking resources if not specified. © December 2009 Altera Corporation Clock Pins or PLL Clock Outputs Can Drive CLK[15..12] Dual-Regional Network CLK[3 ...
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... Outputs CLKn Internal Pin Logic 2 Static Clock Select Enable/ Disable Internal Logic GCLK CLKp CLKn Pin Pin (2) 2 Internal Outputs Logic Static Clock Select (1) Enable/ Disable Internal Logic RCLK Chapter 2: Arria GX Architecture PLLs and Clock Networks (2) © December 2009 Altera Corporation ...
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... Quartus II software. The dynamic clock enable or disable feature allows the internal logic to control power up/down synchronously on GCLK and RCLK nets and PLL_OUT pins. This function is independent of the PLL and is applied directly on the clock network or PLL_OUT pin, as shown in © December 2009 Altera Corporation PLL Counter Outputs (c[5..0]) 6 ...
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... Down to 125-ps increments (3), ( Three differential/six single-ended Chapter 2: Arria GX Architecture PLLs and Clock Networks Enhanced PLLs 10 ( — — — — — — — — — Fast PLL m/(n × post-scale counter) (2) Down to 125-ps increments (3), ( — (6) © December 2009 Altera Corporation ...
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... The connections to the global and regional clocks from the fast PLL outputs, internal drivers, and CLK pins on the left side of the device are shown in Table © December 2009 Altera Corporation Enhanced PLL One single-ended or differential (7), (8) ) period divided by 8 ...
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... The source cannot be driven by internally generated logic before driving the fast PLL. Arria GX Device Handbook, Volume RCLK0 RCLK2 RCLK4 RCLK6 GCLK0 RCLK1 RCLK3 RCLK5 RCLK7 Chapter 2: Arria GX Architecture PLLs and Clock Networks (Note 1) Logic Array Signal Input To Clock Network GCLK2 GCLK1 GCLK3 © December 2009 Altera Corporation ...
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... Drivers from Internal Logic v GCLKDRV0 v GCLKDRV1 GCLKDRV2 — GCLKDRV3 — RCLKDRV0 — RCLKDRV1 — RCLKDRV2 — RCLKDRV3 — RCLKDRV4 — RCLKDRV5 — RCLKDRV6 — © December 2009 Altera Corporation RCLK1 RCLK3 RCLK0 RCLK2 RCLK4 RCLK6 GCLK0 RCLK5 RCLK7 GCLK1 v v — — ...
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... December 2009 Altera Corporation ...
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... If the design uses the feedback input, you might lose one (or two if FBIN is differential) external clock output pin. The connections to the global and regional clocks from the top clock pins and enhanced PLL outputs are shown in the bottom clock pins are shown in © December 2009 Altera Corporation PLL 11 PLL ...
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... December 2009 Altera Corporation ...
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... Enhanced PLL 12 outputs v c0 — — c2 — — c3 — — c4 — — c5 — — © December 2009 Altera Corporation v v — — — — — — — — — — — — — — — v — — ...
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... Affecting All Outputs shows a diagram of the fast PLL. Chapter 2: Arria GX Architecture PLLs and Clock Networks Figure 2–65 shows a From Adjacent PLL Post-Scale Counters /c0 /c1 4 Global Clocks / Regional Clocks /c3 6 I/O Buffers (3) /c4 /c5 to I/O or general routing © December 2009 Altera Corporation ...
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... Programmable pull-up resistors ■ ■ Programmable input and output delays ■ Open-drain outputs ■ DQ and DQS I/O pins DDR registers ■ © December 2009 Altera Corporation VCO Phase Selection Selectable at each PLL Output Port Phase Frequency Detector 8 Charge Loop ÷k ÷ ...
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... There are up to four IOEs per row I/O block and four IOEs per column I/O block. Row I/O blocks drive row, column, or direct link interconnects. Column I/O blocks drive column interconnects. Arria GX Device Handbook, Volume 1 OE Register Register CLK Q Input Register D Input Register D Chapter 2: Arria GX Architecture I/O Structure Q Input Latch ENA © December 2009 Altera Corporation ...
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... December 2009 Altera Corporation C4 Interconnect I/O Block Local ...
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... I/O clocks are generated from global or regional clocks (refer to “PLLs and Clock Networks” on page Arria GX Device Handbook, Volume 1 Vertical I/O Vertical I/O Block Block Contains up to Four IOEs 32 IO_dataina[3..0] io_clk[7..0] IO_datainb[3..0] LAB LAB C4 & C16 Interconnects . 2–66). © December 2009 Altera Corporation Chapter 2: Arria GX Architecture I/O Structure ...
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... Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive the I/O local interconnect, which then drives the control selection multiplexers. © December 2009 Altera Corporation To Other IOEs ...
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... ENA Open-Drain Output CLRN/PRN Input Pin to Logic Array Delay Input Pin to Input Register Delay Input Register D Q ENA CLRN/PRN © December 2009 Altera Corporation Chapter 2: Arria GX Architecture I/O Structure Figure 2–72 shows PCI Clamp (2) V CCIO Programmable Pull-Up Resistor On-Chip Termination ...
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... Figure 2–73 shows an IOE configured for DDR input. input timing diagram. © December 2009 Altera Corporation Quartus II Logic Option Input delay from pin to internal cells Input delay from pin to input register ...
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... To DQS Logic Block (3) I nput Pin to Input RegisterDelay Input Register D Q ENA CLRN/PRN Latch Input Register ENA ENA CLRN/PRN CLRN/PRN Chapter 2: Arria GX Architecture I/O Structure VCCIO PCI Clamp (4) VCCIO Programmable Pull-Up Resistor On-Chip Termination Bus-Hold Circuit Q © December 2009 Altera Corporation ...
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... The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an inverter at the OE register data port. (3) The optional PCI clamp is only available on column I/O pins. © December 2009 Altera Corporation Figure 2–75 shows the IOE configured for DDR shows the DDR output timing diagram ...
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... DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal. Arria GX Device Handbook, Volume (Note 1) Number of Number of ×4 Groups ×8/×9 Groups Chapter 2: Arria GX Architecture I/O Structure Table 2–23 shows the number Number of Number of ×16/×18 Groups ×32/×36 Groups © December 2009 Altera Corporation ...
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... I/O performance. For all I/O standards, the minimum setting is the lowest drive strength that guarantees the I minimum settings provides signal slew rate control to reduce system noise and signal overshoot. © December 2009 Altera Corporation Figure 2–77 shows the phase-shift reference circuit (Note ...
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... Setting (mA) for Column Setting (mA) for Row I/O I/O Pins 24, 20, 16 24, 20, 16, 12 16 12, 10 12, 8 24, 20, 16 12 20, 18, 16, 8 12, 10 12, 10 20, 18, 16 12, 10 20, 18, 16 © December 2009 Altera Corporation Chapter 2: Arria GX Architecture I/O Structure Pins 12 — — — ...
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... HSTL class I and II ■ ■ 1.5-V HSTL class I and II ■ 1.8-V HSTL class I and II ■ SSTL-2 class I and II SSTL-18 class I and II ■ © December 2009 Altera Corporation DC & Switching Characteristics level of the output pin’s bank. CCIO Arria GX Device Handbook, Volume 1 2–93 ...
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... December 2009 Altera Corporation ...
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... On-chip termination simplifies board design by minimizing the number of external termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections. © December 2009 Altera Corporation 1), (2) DQS ×8 DQS × ...
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... HSTL LVDS — — technology OCT & Switching Characteristics OCT, refer to the D chapter. chapter. Chapter 2: Arria GX Architecture I/O Structure Left Bank ( — v — v — OCT is supported across D chapter. High-Speed Differential I/O Interfaces OCT, refer to the DC & D © December 2009 Altera Corporation ...
Page 103
... Arria GX device to drive out, a receiving device powered at a different level can still interface with the Arria GX device if it has inputs that tolerate the V (4) Arria GX devices support 1.2-V HSTL. They do not support 1.2-V LVTTL and 1.2-V LVCMOS. © December 2009 Altera Corporation OCT) S OCT supported by Arria GX devices, refer to the S chapter ...
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... Chapter 2: Arria GX Architecture I/O Structure supplies for the I/O buffers When V is CCIO CCSEL . The ideal case is to CCPD settings for the CCSEL Level shifter required Level shifter Level shifter required required © December 2009 Altera Corporation ...
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... I/O bank (I/O Bank 1 or I/O Bank 2). The second row shows the maximum number of channels that each fast PLL can drive in both I/O banks (I/O Bank 1 and I/O Bank 2). For example, in the 780-pin FineLine BGA EP1AGX20 © December 2009 Altera Corporation Arria GX TDO V Voltage Level in I/O Bank ...
Page 106
... The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels. Arria GX Device Handbook, Volume 1 High-Speed Differential I/O with DPA Support (Note 1) Center Fast PLLs Total Channels PLL1 (Note 1) Center Fast PLLs Total Channels PLL1 © December 2009 Altera Corporation Chapter 2: Arria GX Architecture chapter. PLL2 PLL2 ...
Page 107
... Transmitter 780-pin FineLine BGA Receiver Transmitter 1,152-pin FineLine BGA Receiver Note to Table 2–33: (1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels. © December 2009 Altera Corporation (Note 1) Center Fast PLLs PLL1 PLL2 ...
Page 108
... Arria GX transmitter channel Local diffioclk load_en Chapter 2: Arria GX Architecture High-Speed Differential I/O with DPA Support Corner Fast PLLs PLL2 PLL7 — — 840 Mbps – Dedicated Transmitter Interface Regional or global clock © December 2009 Altera Corporation ...
Page 109
... I/O circuitry provides dedicated data realignment circuitry for user-controlled byte boundary shifting. This simplifies designs while saving ALM resources. You can use an ALM-based state machine to signal the shift of receiver byte boundaries until a specified pattern is detected to indicate byte alignment. © December 2009 Altera Corporation D Q Data Realignment ...
Page 110
... Clock Fast PLL 1 Fast PLL 2 LVDS DPA Quadrant Clock Clock Fast PLL 8 Table 2–30 through Table 2–34. Chapter 2: Arria GX Architecture High-Speed Differential I/O with DPA Support Figure 2–82 shows the (Note 1) Quadrant Quadrant (Note 1) Quadrant Quadrant © December 2009 Altera Corporation ...
Page 111
... Table 2–35. Document Revision History Date and Document Version December 2009, v2.0 May 2008, v1.3 August 2007, v1.2 June 2007, v1.1 May 2007 v1.0 © December 2009 Altera Corporation Changes Made Document template update. ■ Minor text edits. ■ Added “Reverse Serial Pre-CDR Loopback” ...
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... Arria GX Device Handbook, Volume 1 Chapter 2: Arria GX Architecture Document Revision History © December 2009 Altera Corporation ...
Page 113
... JTAG controller. If any of the Stratix, Arria GX, Cyclone, and Cyclone II devices are in the 18th or further position, they will fail configuration. This does not affect the functionality of the SignalTap © December 2009 Altera Corporation 3. Configuration and Testing ® II software or hardware using either jam files (.jam) pins ...
Page 114
... IOE configuration register is loaded and the TAP controller state machine transitions to the UPDATE_DR state. , HIGHZ CLAMP instruction, refer to the MorphIO: An I/O Reconfiguration Solution for Altera Devices Chapter 3: Configuration and Testing IEEE Std. 1149.1 JTAG Boundary-Scan Support Description and pins, TDI ...
Page 115
... Arria GX devices are configured at system power up with data stored in an Altera configuration device or provided by an external controller (for example, a MAX device or microprocessor). You can configure Arria GX devices using the fast passive parallel (FPP), active serial (AS), passive serial (PS), passive parallel asynchronous (PPA), and JTAG configuration schemes ...
Page 116
... VIL and VIH levels driven to CCIO input pin selects which input buffer is used. The 3.3-V/2.5-V CCSEL , while the 1.8-V/1.5-V input buffer is powered by CCPD Chapter 3: Configuration and Testing Configuration “Configuration , the POR time which must be connected to C CPD CCSEL © December 2009 Altera Corporation ...
Page 117
... PS Enhanced configuration device Download cable MAX II device or microprocessor PPA and flash device © December 2009 Altera Corporation input buffer is powered by V CCSEL or ground. A logic high V C CPD voltage of the I/O bank that contains the configuration CCIO to a logic high and the V ...
Page 118
... Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported. (4) The supported download cables include the Altera USB-Blaster universal serial bus (USB) port download cable, MasterBlaster communications cable, ByteBlaster II parallel port download cable, ByteBlasterMV parallel port download cable, and the EthernetBlaster download cable ...
Page 119
... Chapter 3: Configuration and Testing Configuration Configuring Arria GX FPGAs with JRunner The JRunner software driver configures Altera FPGAs, including Arria GX FPGAs, through the ByteBlaster programming input file supported is in Raw Binary File (.rbf) format. JRunner also requires a Chain Description File (.cdf) generated by the Quartus II software. JRunner is targeted for embedded JTAG configuration ...
Page 120
... SRAM bits in the Arria GX FPGA. f For more information about CRC, refer to FPGAs. Arria GX Device Handbook, Volume 1 Chapter 3: Configuration and Testing Automated Single Event Upset (SEU) Detection PLLs in Arria GX Devices AN 357: Error Detection Using CRC in Altera © December 2009 Altera Corporation ...
Page 121
... May 2008 v1.3 August 2007 v1.2 June 2007 v1.1 May 2007 v1.0 © December 2009 Altera Corporation Changes Made Document template update. ■ Minor text edits. ■ Removed “Temperature Sensing ■ Diode” section. Updated Table 3–1 and Table 3–4. ...
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... Arria GX Device Handbook, Volume 1 Chapter 3: Configuration and Testing Document Revision History © December 2009 Altera Corporation ...
Page 123
... Supply voltage CCPD V DC input voltage ( output current, per pin OUT T Storage temperature STG © December 2009 Altera Corporation 4. DC and Switching Characteristics Table 4–42 on page 4–25 provide information on absolute (Note 1), (2), (3) (Part Conditions Minimum With respect to ground –0.5 With respect to ground – ...
Page 124
... J Notes to Table 4–1: (1) For more information about operating requirements for Altera (2) Conditions beyond those listed in Table 4–1 ratings for extended periods of time may have adverse affects on the device. (3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. ...
Page 125
... REFB Note to Table 4–5: (1) The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin. © December 2009 Altera Corporation Conditions For commercial use For industrial use Table 4–2 based upon the input duty cycle. The DC case is equivalent to must rise monotonically from ground to V ...
Page 126
... MHz — — ns 125 ±10% MHz — 50 MHz — — ns — 3125 Mbps — 2.0 V — — V — 3.3 V — — mV 100±15% mV 1200 ± 1200 ± mV 10% 10% 30 — 40 — MHz 50 — © December 2009 Altera Corporation ...
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... On-chip termination resistors Return loss differential mode Return loss common mode Rise time Fall time Intra differential pair skew Intra-transceiver block skew (×4) (13) © December 2009 Altera Corporation –6 Speed Grade Commercial and Industrial Conditions Min Typ BW = Low — Med — ...
Page 128
... Figure 4–2. Chapter 4: DC and Switching Characteristics Operating Conditions Industrial Units Typ Max — 1562.5 MHz 3 — 5 — MHz 9 — 1 — 2 — MHz 4 — — 100 us — 156.25 MHz — Figure 4–1. Figure 4–2 shows the © December 2009 Altera Corporation ...
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... CDR status r x_locktodata Invalid Data r x_dataout CDR LTR Time Figure 4–2. Lock Time Parameters for Automatic Mode CDR status r x_freqlocked r x_dataout © December 2009 Altera Corporation LTR LTD lock time CDR Minimum T1b LTR Invalid data Data lock time from rx_freqlocked 4–7 ...
Page 130
... Condition = 156.25 MHz REFCLK Pattern = CJPAT V = 1200 Pre-emphasis Chapter 4: DC and Switching Characteristics Operating Conditions Positive Channel (p) Negative Channel (n) Ground p − Positive Channel (p) Negative Channel (n) Ground p − –6 Speed Grade Commercial & Units Industrial 0.3 © December 2009 Altera Corporation UI ...
Page 131
... Gigabit Ethernet (GIGE) Receiver Jitter Tolerance Total Jitter Tolerance Deterministic Jitter Tolerance Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Transmitter Jitter Generation Total Transmitter Jitter Generation (TJ) Deterministic Transmitter Jitter Generation (DJ) © December 2009 Altera Corporation (Note 1), (2), (3) (Part Condition = 156.25 MHz ...
Page 132
... Low-Frequency Roll-Off = 100 KHz Chapter 4: DC and Switching Characteristics Operating Conditions –6 Speed Grade Commercial & Units Industrial (6) > 0.65 UI p-p > 0.55 UI p-p > 0.37 UI p-p > 8.5 UI p-p > 1.0 UI p-p > 0.1 UI p-p > 0.1 UI p-p 0.2 UIv 0.3 UI © December 2009 Altera Corporation ...
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... The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3. (7) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification. (8) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M specifications. © December 2009 Altera Corporation (Note 1), (2), ...
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... December 2009 Altera Corporation ...
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... Table 4–11. Typical V V HTX = 1 Typical (mV) OD Table 4–12. Typical Pre-Emphasis (First Post-Tap), V HTX = 1 Setting (mV) OD 400 600 800 © December 2009 Altera Corporation Receiver PCS Latency 4–5 — 11–13 1 — 4–5 — — 1 — 2–2.5 — 5.5–6.5 0.5 — ...
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... Typ Max Units A –10 — 10 A –10 — 10 — 0.30 (3) A — 0.50 (3) A — 0.62 (3) A — 2.7 (3) mA — 3.6 (3) mA — 4.3 (3) mA — 4.0 (3) mA — 4.0 (3) mA — 4.0 (3) mA © December 2009 Altera Corporation ...
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... OL Notes to Table 4–16: (1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. (2) This specification is supported across all the programmable drive strength available for this I/O standard. © December 2009 Altera Corporation (Note 1) Conditions Device 3.3 V — ...
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... V — 0.4 V Maximum Units 1.71 1.89 V 2.25 V CCIO –0.3 0.35 × CCIO – 0.45 — V CCIO — 0.45 V Arria GX Architecture Maximum Units 1.425 1.575 0.3 V CCIO CCIO –0.3 0. CCIO — V CCIO — 0. CCIO Arria GX © December 2009 Altera Corporation ...
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... CCIO banks ( and 6) V Input differential voltage swing ID (single-ended) V Input common mode voltage ICM V Output differential voltage (single-ended Output common mode voltage OCM R Receiver differential input discrete L resistor (external to Arria GX devices) © December 2009 Altera Corporation (Peak-to-Peak Conditions Minimum — 2.375 — ...
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... R 525 — 100 R 1,650 — L — 90 100 , not V . The PLL clock output/feedback CCINT CCIO © December 2009 Altera Corporation Operating Conditions Maximum Units 3.465 V 900 mV 1,800 mV 710 mV 1,570 mV 110 Units ...
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... Termination voltage TT V (DC) High-level DC input voltage IH V (DC) Low-level DC input voltage (AC) High-level AC input voltage IH V (AC) Low-level AC input voltage IL © December 2009 Altera Corporation Conditions Minimum Typical — 3.0 3.3 — 0.5 V — CCIO — –0.3 — = –500 A I 0.9 V — OUT CCIO = 1,500 ...
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... Units 2.5 2.625 0.04 V REF REF 1.313 V — 3.0 V — V – 0.18 V REF — — V — V – 0.35 V REF — V — V – 0. Arria GX Architecture Maximum Units 2.5 2.625 0.04 V REF REF 1.25 1.313 V — 0.3 V CCIO © December 2009 Altera Corporation ...
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... High-level DC input voltage IH V (DC) Low-level DC input voltage IL V (AC) High-level AC input voltage IH V (AC) Low-level AC input voltage IL V High-level output voltage OH V Low-level output voltage OL © December 2009 Altera Corporation Conditions Minimum Typical — –0.3 — 0.35 REF — — –16 16.4 mA (1) — ...
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... OH Minimum Typical Maximum 1.425 1.5 1.575 0.2 — — 0.68 — 0.9 0.4 — — 0.68 — 0.9 © December 2009 Altera Corporation Operating Conditions Maximum Units 1.575 V 0.788 V 0.788 V — — V — V – 0.1 V REF — — V — ...
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... V (DC) DC input differential voltage DIF V (DC) DC common mode input voltage CM V (AC) AC differential input voltage DIF V (AC) AC differential cross point voltage OX © December 2009 Altera Corporation Conditions Minimum Typical — 1.71 1.80 — 0.85 0.90 — 0.85 0.90 — 0.1 REF — ...
Page 146
... V Resistance Tolerance Industrial Units Max Max ±30 ±30 % ±30 ± ±30 ±30 % ±30 ±30 % ±36 ±36 % ±50 ±50 % © December 2009 Altera Corporation ...
Page 147
... Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within ±0.5 pF. Power Consumption Altera offers two ways to calculate power for a design: the Excel-based PowerPlay early power estimator power calculator and the Quartus II PowerPlay power analyzer feature. The interactive Excel-based PowerPlay Early Power Estimator is typically used prior to designing the FPGA in order to get an estimate of device power ...
Page 148
... Table 4–43 lists the status of the Arria GX device timing Preliminary Correlated — — — — — — — — — — Chapter 4: DC and Switching Characteristics I/O Timing Model PowerPlay Early Power PowerPlay Power Analysis chapter . Final © December 2009 Altera Corporation ...
Page 149
... I/O Timing Measurement Methodology Different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination for each I/O standard and with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the timing is specified up to the output pin of the FPGA device. The Quartus II software calculates the I/O timing for each I/O standard with a default baseline loading as specified by the I/O standards ...
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... December 2009 Altera Corporation ...
Page 151
... V, less than 50-mV ripple on V CCPD Figure 4–8 and enable timing. Figure 4–8. Measurement Setup for t OE Din OE Din Note to Figure 4–8: ( 1.12 V for this measurement. CCINT © December 2009 Altera Corporation (Note 1), (2), Loading and Termination V CCIO ...
Page 152
... V CCINT “1” ½ V CCIO Enable ½ V CCINT “0” ½ CCIO zl (Part Measurement Point VMEAS (V) 1.5675 1.5675 1.1875 0.855 0.7125 1.485 1.485 1.1625 1.1625 0.83 0.83 0.83 0.83 0.6875 0.6875 0.570 1.1625 1.1625 0.83 © December 2009 Altera Corporation ...
Page 153
... This is in addition to intra-clock network skew, which is modeled in the Quartus II software. Default Capacitive Loading of Different I/O Standards See Table 4–47 Table 4–47. Default Loading of Different I/O Standards for Arria GX Devices (Part I/O Standard LVTTL LVCMOS 2.5 V © December 2009 Altera Corporation (Note 1), (2), (3), Measurement Conditions V (V) V (V) Edge Rate (ns) ...
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... I/O pin timing for Arria GX devices. I/O are reported for the cases when I/O clock is driven Table 4–51 show the maximum I/O timing parameters for Chapter 4: DC and Switching Characteristics Typical Design Performance Units © December 2009 Altera Corporation ...
Page 155
... LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V GCLK PLL GCLK 1.5 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL © December 2009 Altera Corporation Fast Corner –6 Speed Industrial Commercial 0.117 0.117 0.011 0.011 –0.117 –0.117 –0.011 –0.011 Fast Corner ...
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... December 2009 Altera Corporation ...
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... GCLK GCLK PLL 1 GCLK GCLK PLL 1 GCLK GCLK PLL 1 GCLK GCLK PLL 1 GCLK GCLK PLL 1 GCLK GCLK PLL © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 1.106 1.106 SU t –1.001 –1.001 H t 2.530 2.530 SU t –2.425 –2.425 H Fast Model ...
Page 158
... Speed Units Grade 5.614 ns 2.542 ns 5.538 ns 2.466 ns 5.407 ns 2.335 ns 5.556 ns 2.484 ns 5.485 ns 2.413 ns 5.468 ns 2.396 ns 5.447 ns 2.375 ns 5.466 ns 2.394 ns 5.430 ns 2.358 ns 5.426 ns 2.354 ns 5.415 ns 2.343 ns 5.414 ns 2.342 ns 5.443 ns 2.371 ns 5.429 ns 2.357 ns 5.421 ns 2.349 ns 5.613 ns 2.530 ns © December 2009 Altera Corporation ...
Page 159
... GCLK PLL GCLK 2 GCLK PLL GCLK 2 GCLK PLL GCLK 2 GCLK PLL GCLK 1 GCLK PLL GCLK 1 GCLK PLL © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 2.909 2.909 CO t 1.467 1.467 CO t 2.764 2.764 CO t 1.322 1.322 CO t 2.697 2 ...
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... December 2009 Altera Corporation ...
Page 161
... GCLK PLL GCLK 1.5-V HSTL 16 mA CLASS II GCLK PLL GCLK 1.5-V HSTL 18 mA CLASS II GCLK PLL GCLK 1.5-V HSTL 20 mA CLASS II GCLK PLL © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 2.609 2.609 CO t 1.164 1.164 CO t 2.605 2.605 ...
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... Typical Design Performance –6 Speed Units Grade 5.791 ns 2.685 ns 5.791 ns 2.685 ns 6.969 ns 3.880 ns –6 Speed Grade Units 0.273 ns 0.019 ns –0.273 ns –0.019 ns –6 Speed Grade Units 0.223 ns –0.008 ns –0.224 ns 2.658 ns © December 2009 Altera Corporation ...
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... GCLK 1.5 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL © December 2009 Altera Corporation Table 4–57 list the maximum I/O timing parameters for Fast Model Parameter Industrial Commercial t 1.561 1.561 SU t –1.456 – ...
Page 164
... Speed Units Grade 2.915 ns –2.638 ns 6.021 ns –5.744 ns 2.915 ns –2.638 ns 6.021 ns –5.744 ns © December 2009 Altera Corporation ...
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... SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK SSTL-18 CLASS II GCLK PLL GCLK 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 1.261 1.261 SU t –1.156 –1.156 ...
Page 166
... Speed Units Grade 2.904 6.699 ns 1.485 3.627 ns 2.776 6.059 ns 1.357 2.987 ns 2.720 6.022 ns 1.301 2.950 ns 2.776 6.059 ns 1.357 2.987 ns 2.670 5.753 ns 1.251 2.681 ns 2.759 6.033 ns 1.340 2.961 ns © December 2009 Altera Corporation ...
Page 167
... GCLK PLL GCLK 1.8-V HSTL 6 mA CLASS I GCLK PLL GCLK 1.8-V HSTL 8 mA CLASS I GCLK PLL GCLK 1.8-V HSTL 10 mA CLASS I GCLK PLL © December 2009 Altera Corporation Fast Model Parameter Industrial Commercial t 2.656 2.656 CO t 1.237 1.237 CO t 2.637 2.637 ...
Page 168
... Speed Units Grade 6.541 ns 3.435 ns 6.169 ns 3.063 ns 6.169 ns 3.063 ns 6.000 ns 2.894 ns 5.875 ns 2.769 ns 5.877 ns 2.771 ns 6.169 ns 3.063 ns 5.874 ns 2.768 ns 5.796 ns 2.690 ns 5.764 ns 2.658 ns 5.746 ns 2.640 ns © December 2009 Altera Corporation ...
Page 169
... GCLK CLASS I GCLK PLL SSTL GCLK CLASS I GCLK PLL SSTL GCLK CLASS II GCLK PLL SSTL GCLK CLASS II GCLK PLL © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 2.627 2.627 CO t 1.185 1.185 CO t 2.726 2.726 CO t 1.284 1.284 ...
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... December 2009 Altera Corporation ...
Page 171
... Arria GX devices. Table 4–58. EP1AGX35 Row Pin Delay Adders for Regional Clock Parameter RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 2.633 2.633 ...
Page 172
... Chapter 4: DC and Switching Characteristics Typical Design Performance –6 Speed Grade Units 0.254 ns –0.01 ns –0.244 ns 3.133 ns –6 Speed Units Grade 3.542 ns –3.265 ns 6.626 ns –6.349 ns 3.542 ns –3.265 ns 6.626 ns –6.349 ns 3.523 ns –3.246 ns 6.607 ns –6.330 ns 3.730 ns –3.453 ns 6.814 ns –6.537 ns 3.825 ns –3.548 ns 6.909 ns –6.632 ns © December 2009 Altera Corporation ...
Page 173
... GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL GCLK 1.5-V HSTL CLASS I GCLK PLL GCLK 1.5-V HSTL CLASS II GCLK PLL GCLK LVDS GCLK PLL © December 2009 Altera Corporation Fast Model Industrial Commercial t 1.375 1.375 SU t –1.270 –1.270 H t 2.802 2.802 SU t – ...
Page 174
... December 2009 Altera Corporation ...
Page 175
... Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part Drive I/O Standard Clock Strength 3.3-V LVTTL 4 mA GCLK GCLK PLL 3.3-V LVTTL 8 mA GCLK GCLK PLL © December 2009 Altera Corporation Fast Corner Industrial Commercial t 1.104 1.104 SU t –0.999 –0.999 H t 2.546 2 ...
Page 176
... December 2009 Altera Corporation ...
Page 177
... LVTTL 16 mA GCLK GCLK PLL 3.3-V LVTTL 20 mA GCLK GCLK PLL 3.3-V LVTTL 24 mA GCLK GCLK PLL 3.3 GCLK LVCMOS GCLK PLL © December 2009 Altera Corporation Fast Model Parameter Industrial Commercial t 2.606 2.606 CO t 1.178 1.178 CO t 2.608 2.608 ...
Page 178
... December 2009 Altera Corporation ...
Page 179
... GCLK PLL 1.8-V HSTL 8 mA GCLK CLASS I GCLK PLL 1.8-V HSTL 10 mA GCLK CLASS I GCLK PLL 1.8-V HSTL 12 mA GCLK CLASS I GCLK PLL © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 2.648 2.648 CO t 1.202 1.202 CO t 2.628 2.628 ...
Page 180
... EP1AGX50 regional clock (RCLK) adder values that Typical Design Performance –6 Speed Units Grade 5.574 ns 2.314 ns 5.578 ns 2.325 ns 5.577 ns 2.334 ns 5.675 ns 2.569 ns 5.651 ns 2.554 ns 5.653 ns 2.556 ns 5.655 ns 2.558 ns 5.653 ns 2.556 ns 5.573 ns 2.368 ns 5.571 ns 2.378 ns 5.581 ns 2.391 ns 5.803 ns 2.697 ns 5.803 ns 2.697 ns 6.969 ns 3.880 ns © December 2009 Altera Corporation ...
Page 181
... Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part I/O Standard Clock GCLK 3.3-V LVTTL GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL © December 2009 Altera Corporation Fast Corner Industrial Commercial 0.151 0.151 0.011 0.011 –0.151 –0.151 –0.011 –0.011 ...
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... December 2009 Altera Corporation ...
Page 183
... GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V GCLK PLL GCLK 1.5 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL © December 2009 Altera Corporation Fast Model Parameter Industrial Commercial t 1.281 1.281 SU t –1.176 –1.176 H t 2.853 2.853 ...
Page 184
... December 2009 Altera Corporation ...
Page 185
... GCLK GCLK PLL 1 GCLK GCLK PLL 1 GCLK GCLK PLL 2 mA GCLK 1.5 V GCLK PLL 4 mA GCLK 1.5 V GCLK PLL © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 0.980 0.980 SU t –0.875 –0.875 H t 2.557 2.557 SU t –2.452 –2.452 ...
Page 186
... Speed Units Grade 6.057 ns 2.633 ns 5.981 ns 2.557 ns 5.850 ns 2.426 ns 6.025 ns 2.582 ns 5.954 ns 2.511 ns 5.937 ns 2.494 ns 5.916 ns 2.473 ns 5.935 ns 2.492 ns 5.899 ns 2.456 ns 5.895 ns 2.452 ns 5.884 ns 2.441 ns 5.883 ns 2.440 ns 5.912 ns 2.469 ns 5.898 ns 2.455 ns 5.890 ns 2.447 ns 6.037 ns 2.618 ns © December 2009 Altera Corporation ...
Page 187
... GCLK GCLK PLL 2 GCLK GCLK PLL 2 GCLK GCLK PLL 2 GCLK GCLK PLL 1 GCLK GCLK PLL 1 GCLK GCLK PLL © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 3.036 3.036 CO t 1.466 1.466 CO t 2.891 2.891 CO t 1.321 1.321 CO t 2.824 2 ...
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... December 2009 Altera Corporation ...
Page 189
... GCLK PLL 16 mA GCLK 1.5-V HSTL CLASS II GCLK PLL 18 mA GCLK 1.5-V HSTL CLASS II GCLK PLL 20 mA GCLK 1.5-V HSTL CLASS II GCLK PLL © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 2.737 2.737 CO t 1.164 1.164 CO t 2.733 2.733 ...
Page 190
... I/O timing parameters for Typical Design Performance –6 Speed Units Grade 6.213 ns 2.778 ns 6.213 ns 2.778 ns 7.396 ns 3.973 ns –6 Speed Grade Units 0.311 ns –0.006 ns –0.311 ns 0.006 ns –6 Speed Grade Units 0.344 ns –2.338 ns –0.343 ns 4.486 ns © December 2009 Altera Corporation ...
Page 191
... GCLK 1.5 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK SSTL-18 CLASS II GCLK PLL © December 2009 Altera Corporation Fast Model Parameter Industrial Commercial t 1.295 1.295 SU t –1.190 –1.190 H t 3.366 3 ...
Page 192
... Speed Units Grade 2.290 ns –2.013 ns 6.425 ns –6.148 ns 2.290 ns –2.013 ns 6.425 ns –6.148 ns 2.272 ns –1.995 ns 6.407 ns –6.130 ns © December 2009 Altera Corporation ...
Page 193
... SSTL-18 CLASS I GCLK PLL GCLK SSTL-18 CLASS II GCLK PLL GCLK 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL GCLK 1.5-V HSTL CLASS I GCLK PLL © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 1.094 1.094 SU t –0.989 –0.989 ...
Page 194
... Speed Units Grade 3.170 7.382 ns 1.099 3.238 ns 3.042 6.742 ns 0.971 2.598 ns 2.986 6.705 ns 0.915 2.561 ns 3.042 6.742 ns 0.971 2.598 ns 2.936 6.436 ns 0.865 2.292 ns 3.025 6.716 ns 0.954 2.572 ns 2.922 6.458 ns 0.851 2.314 ns 2.903 6.344 ns 0.832 2.200 ns © December 2009 Altera Corporation ...
Page 195
... GCLK PLL 10 mA GCLK 1.8-V HSTL CLASS I GCLK PLL 12 mA GCLK 1.8-V HSTL CLASS I GCLK PLL 4 mA GCLK 1.5-V HSTL CLASS I GCLK PLL © December 2009 Altera Corporation Fast Model Parameter Industrial Commercial t 3.087 3.087 CO t 1.034 1.034 CO t 3.076 3.076 ...
Page 196
... Speed Units Grade 7.164 ns 3.029 ns 6.792 ns 2.657 ns 6.792 ns 2.657 ns 6.623 ns 2.488 ns 6.498 ns 2.363 ns 6.500 ns 2.365 ns 6.792 ns 2.657 ns 6.497 ns 2.362 ns 6.419 ns 2.284 ns 6.387 ns 2.252 ns 6.369 ns 2.234 ns 6.347 ns 2.212 ns 6.824 ns 2.689 ns © December 2009 Altera Corporation ...
Page 197
... GCLK CLASS II GCLK PLL SSTL GCLK CLASS II GCLK PLL SSTL GCLK CLASS II GCLK PLL SSTL- GCLK CLASS I GCLK PLL © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 2.906 2.906 CO t 0.842 0.842 CO t 2.885 2.885 CO t 0.821 0.821 ...
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... December 2009 Altera Corporation ...
Page 199
... Arria GX devices. Table 4–76. EP1AGX90 Row Pin Delay Adders for Regional Clock Parameter RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder © December 2009 Altera Corporation Fast Corner Parameter Industrial Commercial t 2.845 2.845 ...
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... Fast Model Industrial Commercial 1.394 1.394 1.399 1.399 –0.027 –0.027 –0.022 –0.022 Chapter 4: DC and Switching Characteristics Typical Design Performance –6 Speed Grade Units 0.354 ns –3.607 ns –0.353 ns 5.188 ns –6 Speed Grade Units 3.161 ns 3.155 ns 0.091 ns 0.085 ns © December 2009 Altera Corporation ...