EP2S90F1020I4N

Manufacturer Part NumberEP2S90F1020I4N
DescriptionIC STRATIX II FPGA 90K 1020-FBGA
ManufacturerAltera
SeriesStratix® II
EP2S90F1020I4N datasheet
 

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells90960Number Of Labs/clbs4548
Total Ram Bits4520488Number Of I /o758
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case1020-FBGA
Family NameStratix IINumber Of Logic Blocks/elements90960
# I/os (max)758Frequency (max)711.24MHz
Process Technology90nm (CMOS)Operating Supply Voltage (typ)1.2V
Logic Cells90960Ram Bits4520488
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count1020
Package TypeFC-FBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1920
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Document Revision History
Document
Table 2–27
Revision History
Table 2–27. Document Revision History (Part 1 of 2)
Date and
Document
Version
May 2007, v4.3 Updated
“Clock Control Block”
Updated note in the
Deleted Tables 2-11 and 2-12.
Updated notes to:
Figure 2–41
Figure 2–42
Figure 2–43
Figure 2–45
Updated notes to
Moved Document Revision History to end of the chapter.
August 2006,
Updated Table 2–18 with note.
v4.2
April 2006,
Updated Table 2–13.
v4.1
Removed Note 2 from Table 2–16.
Updated “On-Chip Termination” section and Table 2–19 to
include parallel termination with calibration information.
Added new “On-Chip Parallel Termination with Calibration”
section.
Updated Figure 2–44.
December
Updated “Clock Control Block” section.
2005, v4.0
July 2005, v3.1
Updated HyperTransport technology information in Table 2–18.
Updated HyperTransport technology information in
Figure 2–57.
Added information on the asynchronous clear signal.
May 2005, v3.0
Updated “Functional Description” section.
Updated Table 2–3.
Updated “Clock Control Block” section.
Updated Tables 2–17 through 2–19.
Updated Tables 2–20 through 2–22.
Updated Figure 2–57.
March 2005,
Updated “Functional Description” section.
2.1
Updated Table 2–3.
2–104
Stratix II Device Handbook, Volume 1
shows the revision history for this chapter.
Changes Made
section.
“Clock Control Block”
section.
Table
2–18.
Summary of Changes
Added parallel on-
chip termination
description and
specification.
Changed RCLK
names to match the
Quartus II software in
Table 2–13.
Altera Corporation
May 2007