EP2S90F1020I4N | |
|---|---|
| Manufacturer Part Number | EP2S90F1020I4N |
| Description | IC STRATIX II FPGA 90K 1020-FBGA |
| Manufacturer | Altera |
| Series | Stratix® II |
| EP2S90F1020I4N datasheet |
|
Specifications of EP2S90F1020I4N | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 90960 | Number Of Labs/clbs | 4548 |
| Total Ram Bits | 4520488 | Number Of I /o | 758 |
| Voltage - Supply | 1.15 V ~ 1.25 V | Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 100°C | Package / Case | 1020-FBGA |
| Family Name | Stratix II | Number Of Logic Blocks/elements | 90960 |
| # I/os (max) | 758 | Frequency (max) | 711.24MHz |
| Process Technology | 90nm (CMOS) | Operating Supply Voltage (typ) | 1.2V |
| Logic Cells | 90960 | Ram Bits | 4520488 |
| Operating Supply Voltage (min) | 1.15V | Operating Supply Voltage (max) | 1.25V |
| Operating Temp Range | -40C to 100C | Operating Temperature Classification | Industrial |
| Mounting | Surface Mount | Pin Count | 1020 |
| Package Type | FC-FBGA | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
| Number Of Gates | - | Other names | 544-1920 EP2S90F1020I4N |
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
PrevNext
Timing Model
EP2S15 Clock Timing Parameters
Tables 5–44
EP2S15 devices.
Table 5–44. EP2S15 Column Pins Regional Clock Timing Parameters
Minimum Timing
Parameter
Industrial
t
1.445
C I N
t
1.288
C O U T
t
0.104
P L L C I N
t
-0.053
P L L C O U T
Table 5–45. EP2S15 Column Pins Global Clock Timing Parameters
Minimum Timing
Parameter
Industrial
t
1.419
C I N
t
1.262
C O U T
t
0.094
P L L C I N
t
-0.063
P L L C O U T
Table 5–46. EP2S15 Row Pins Regional Clock Timing Parameters
Minimum Timing
Parameter
Industrial
t
1.232
C I N
t
1.237
C O U T
t
-0.109
P L L C I N
t
-0.104
P L L C O U T
5–42
Stratix II Device Handbook, Volume 1
though
5–47
show the maximum clock timing parameters for
-3 Speed
Grade
Commercial
1.512
2.487
1.347
2.245
0.102
0.336
-0.063
0.094
-3 Speed
Grade
Commercial
1.487
2.456
2.813
1.322
2.214
2.535
0.092
0.326
0.363
-0.073
0.084
0.085
-3 Speed
Grade
Commercial
1.288
2.144
1.293
2.140
-0.122
-0.007
-0.117
-0.011
-4 Speed
-5 Speed
Unit
Grade
Grade
2.848
3.309
ns
2.570
2.985
ns
0.373
0.424
ns
0.095
0.1
ns
-4 Speed
-5 Speed
Unit
Grade
Grade
3.273
ns
2.949
ns
0.414
ns
0.09
ns
-4 Speed
-5 Speed
Unit
Grade
Grade
2.454
2.848
ns
2.450
2.843
ns
-0.021
-0.037
ns
-0.025
-0.042
ns
Altera Corporation
April 2011
Related parts for EP2S90F1020I4N | ||||
|---|---|---|---|---|
| Part Number | Description | Manufacturer | Datasheet | Request |
 DK-CYCII-2C20N |
CYCLONE II STARTER KIT EP2C20N | Altera |
| |
 EP1AGX50DF780I6 |
ALTERA | Altera | ||
 AN209 |
Altera Corporation |
| ||
|
EP610PC-35 |
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP | Altera Corporation |
| |
|
EP610PC-15 |
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP | Altera Corporation |
| |
|
EP610IPC-25 |
Altera Corporation |
| ||
|
EP610PC-30 |
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP | Altera Corporation |
| |
|
EP220PC-10 |
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns | Altera Corporation |
| |
|
EP220PC-7 |
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns | Altera Corporation |
| |
|
EP220PC-12 |
Classic EPLD | Altera Corporation |
| |
|
EP220PC-10A |
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns | Altera Corporation |
| |
|
P85C224-66 |
Altera Corporation |
| ||
|
EP320PC |
Altera Corporation |
| ||
|
EP2A15B724C7 |
Altera Corporation |
| ||
|
EP610PC-25T |
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP | Altera Corporation |
|
