EP2S90F1020I4N

Manufacturer Part NumberEP2S90F1020I4N
DescriptionIC STRATIX II FPGA 90K 1020-FBGA
ManufacturerAltera
SeriesStratix® II
EP2S90F1020I4N datasheet
 

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells90960Number Of Labs/clbs4548
Total Ram Bits4520488Number Of I /o758
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case1020-FBGA
Family NameStratix IINumber Of Logic Blocks/elements90960
# I/os (max)758Frequency (max)711.24MHz
Process Technology90nm (CMOS)Operating Supply Voltage (typ)1.2V
Logic Cells90960Ram Bits4520488
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count1020
Package TypeFC-FBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1920
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Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II DDIO
row output clock on a –3 device ranges from 48.4% to 51.6%.
Table 5–83. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 & -5
Devices
Notes
(1),
(2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock
Row DDIO Output I/O
Standard
TTL/CMOS
3.3/2.5 V
3.3-V LVTTL
440
3.3-V LVCMOS
390
2.5 V
375
1.8 V
325
1.5-V LVCMOS
430
SSTL-2 Class I
355
SSTL-2 Class II
350
SSTL-18 Class I
335
1.8-V HSTL Class I
330
1.5-V HSTL Class I
330
LVDS/ HyperTransport
180
technology
Notes to
Table
5–83:
(1)
Table 5–83
assumes the input clock has zero DCD.
(2)
The DCD specification is based on a no logic array noise condition.
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 1 of 2)
Notes
(1),
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
DDIO Column Output I/O
Standard
3.3/2.5 V
3.3-V LVTTL
260
3.3-V LVCMOS
210
2.5 V
195
Altera Corporation
April 2011
Port (No PLL in the Clock Path)
SSTL-2
SSTL/HSTL
1.8/1.5 V
2.5 V
1.8/1.5 V
495
170
450
120
430
105
385
90
490
160
410
85
405
80
390
65
385
60
390
60
180
180
(2)
Clock Port (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
1.8/1.5 V
2.5 V
380
145
330
100
315
85
DC & Switching Characteristics
LVDS/
Unit
HyperTransport
Technology
3.3 V
160
105
ps
110
75
ps
95
90
ps
100
135
ps
155
100
ps
75
85
ps
70
90
ps
65
105
ps
70
110
ps
70
105
ps
180
180
ps
1.2-V
Unit
SSTL/HSTL
HSTL
1.8/1.5 V
1.2 V
145
145
ps
100
100
ps
85
85
ps
Stratix II Device Handbook, Volume 1
5–83