EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 224

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EP2S90F1020I4N

Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N
High-Speed I/O Specifications
Table 5–89. High-Speed I/O Specifications for -3 Speed Grade (Part 2 of 2)
Symbol
f
(data rate)
J = 4 to 10 (LVDS, HyperTransport technology)
H S D R
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
f
(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
H S D R D PA
TCCS
All differential standards
SW
All differential standards
Output jitter
Output t
All differential I/O standards
R I S E
Output t
All differential I/O standards
FA L L
t
DUTY
DPA run length
DPA jitter tolerance
Data channel peak-to-peak jitter
DPA lock time
Standard
SPI-4
Parallel Rapid I/O
Miscellaneous
Notes to
Table
5–89:
(1)
When J = 4 to 10, the SERDES block is used.
(2)
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
(3)
frequency × W ≤ 1,040.
(4)
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
5–88
Stratix II Device Handbook, Volume 1
-3 Speed Grade
Conditions
Min
150
(4)
(4)
150
-
330
45
0.44
Training
Transition
Pattern
Density
0000000000
10%
256
1111111111
00001111
25%
256
10010000
50%
256
10101010
100%
256
01010101
256
Notes
(1),
(2)
Unit
Typ
Max
1,040
Mbps
760
Mbps
500
Mbps
1,040
Mbps
200
ps
-
ps
190
ps
160
ps
180
ps
50
55
%
6,400
UI
UI
Number of
repetitions
Altera Corporation
April 2011

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