EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 3

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EP2S90F1020I4N

Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N

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Introduction
Features
Altera Corporation
May 2007
SII51001-4.2
The Stratix
SRAM process and features a new logic structure that maximizes
performance, and enables device densities approaching 180,000
equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of
on-chip, TriMatrix™ memory for demanding, memory intensive
applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit)
multipliers for efficient implementation of high performance filters and
other DSP functions. Various high-speed external memory interfaces are
supported, including double data rate (DDR) SDRAM and DDR2
SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data
rate (SDR) SDRAM. Stratix II devices support various I/O standards
along with support for 1-gigabit per second (Gbps) source synchronous
signaling with DPA circuitry. Stratix II devices offer a complete clock
management solution with internal clock frequency of up to 550 MHz
and up to 12 phase-locked loops (PLLs). Stratix II devices are also the
industry’s first FPGAs with the ability to decrypt a configuration
bitstream using the Advanced Encryption Standard (AES) algorithm to
protect designs.
The Stratix II family offers the following features:
15,600 to 179,400 equivalent LEs; see
New and innovative adaptive logic module (ALM), the basic
building block of the Stratix II architecture, maximizes performance
and resource usage efficiency
Up to 9,383,040 RAM bits (1,172,880 bytes) available without
reducing logic resources
TriMatrix memory consisting of three RAM block sizes to implement
true dual-port memory and first-in first-out (FIFO) buffers
High-speed DSP blocks provide dedicated implementation of
multipliers (at up to 450 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
Up to 16 global clocks with 24 clocking resources per device region
Clock control blocks support dynamic clock network enable/disable,
which allows clock networks to power down to reduce power
consumption in user mode
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device
provide spread spectrum, programmable bandwidth, clock switch-
over, real-time PLL reconfiguration, and advanced multiplication
and phase shifting
®
II FPGA family is based on a 1.2-V, 90-nm, all-layer copper
Table 1–1
1. Introduction
1–1

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