EP2S90F1020I4N

Manufacturer Part NumberEP2S90F1020I4N
DescriptionIC STRATIX II FPGA 90K 1020-FBGA
ManufacturerAltera
SeriesStratix® II
EP2S90F1020I4N datasheet
 

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells90960Number Of Labs/clbs4548
Total Ram Bits4520488Number Of I /o758
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case1020-FBGA
Family NameStratix IINumber Of Logic Blocks/elements90960
# I/os (max)758Frequency (max)711.24MHz
Process Technology90nm (CMOS)Operating Supply Voltage (typ)1.2V
Logic Cells90960Ram Bits4520488
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count1020
Package TypeFC-FBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1920
EP2S90F1020I4N
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Stratix II devices are available in space-saving FineLine BGA
(see
Table 1–2. Stratix II Package Options & I/O Pin Counts
484-Pin
Device
FineLine BGA
EP2S15
342
EP2S30
342
EP2S60
(3)
334
EP2S90
(3)
(3)
EP2S130
EP2S180
(3)
Notes to
Table
1–2:
(1)
All I/O pin counts include eight dedicated clock input pins (clk1p, clk1n, clk3p, clk3n, clk9p, clk9n,
clk11p, and clk11n) that can be used for data inputs.
(2)
The Quartus II software I/O pin counts include one additional pin,
purpose I/O pins. The PLL_ENA pin can only be used to enable the PLLs within the device.
(3)
The I/O pin counts for the EP2S60, EP2S90, EP2S130, and EP2S180 devices in the 1020-pin and 1508-pin packages
include eight dedicated fast PLL clock inputs (FPLL7CLKp/n, FPLL8CLKp/n, FPLL9CLKp/n, and
FPLL10CLKp/n) that can be used for data inputs.
Table 1–3. Stratix II FineLine BGA Package Sizes
Dimension
484 Pin
Pitch (mm)
1.00
Area (mm2)
529
Length × width
23 × 23
(mm × mm)
All Stratix II devices support vertical migration within the same package
(for example, you can migrate between the EP2S15, EP2S30, and EP2S60
devices in the 672-pin FineLine BGA package). Vertical migration means
that you can migrate to devices whose dedicated pins, configuration pins,
and power pins are the same for a given package across device densities.
To ensure that a board layout supports migratable densities within one
package offering, enable the applicable vertical migration path within the
Quartus II software (Assignments menu > Device > Migration Devices).
Altera Corporation
May 2007
Tables 1–2
and 1–3).
Notes
(1),
484-Pin
672-Pin
780-Pin
Hybrid
FineLine
FineLine
FineLine
BGA
BGA
BGA
366
500
492
308
534
534
PLL_ENA
484-Pin
672 Pin
780 Pin
Hybrid
1.00
1.00
729
729
27 × 27
27 × 27
29 × 29
Introduction
®
packages
(2)
1,020-Pin
1,508-Pin
FineLine BGA
FineLine BGA
718
758
902
742
1,126
742
1,170
, which is not available as general-
1,020 Pin
1,508 Pin
1.00
1.00
1.00
841
1,089
1,600
33 × 33
40 × 40
Stratix II Device Handbook, Volume 1
1–3