EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 50

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EP2S90F1020I4N

Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N
Digital Signal Processing Block
Table 2–5
Table 2–5. DSP Blocks in Stratix II Devices
Device
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
Note to
(1)
DSP block multipliers can optionally feed an adder/subtractor or
accumulator in the block depending on the configuration. This makes
routing to ALMs easier, saves ALM routing resources, and increases
performance, because all connections and blocks are in the DSP block.
Additionally, the DSP block input registers can efficiently implement shift
registers for FIR filter applications, and DSP blocks support Q1.15 format
rounding and saturation.
Figure 2–28
18 × 18-bit multiplier mode.
2–42
Stratix II Device Handbook, Volume 1
shows the number of DSP blocks in each Stratix II device.
Total 9 × 9
DSP Blocks
Multipliers
12
96
16
128
36
288
48
384
63
504
96
768
Table
2–5:
Each device has either the numbers of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
shows the top-level diagram of the DSP block configured for
Note (1)
Total 18 × 18
Total 36 × 36
Multipliers
Multipliers
48
12
64
16
144
36
192
48
252
63
384
96
Altera Corporation
May 2007

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