EP2S90F1020I4N

Manufacturer Part NumberEP2S90F1020I4N
DescriptionIC STRATIX II FPGA 90K 1020-FBGA
ManufacturerAltera
SeriesStratix® II
EP2S90F1020I4N datasheet
 

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells90960Number Of Labs/clbs4548
Total Ram Bits4520488Number Of I /o758
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case1020-FBGA
Family NameStratix IINumber Of Logic Blocks/elements90960
# I/os (max)758Frequency (max)711.24MHz
Process Technology90nm (CMOS)Operating Supply Voltage (typ)1.2V
Logic Cells90960Ram Bits4520488
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count1020
Package TypeFC-FBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1920
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I/O Structure
Table 2–14. DQS & DQ Bus Mode Support (Part 2 of 2)
Device
Package
EP2S90
484-pin Hybrid FineLine BGA
780-pin FineLine BGA
1,020-pin FineLine BGA
1,508-pin FineLine BGA
EP2S130 780-pin FineLine BGA
1,020-pin FineLine BGA
1,508-pin FineLine BGA
EP2S180 1,020-pin FineLine BGA
1,508-pin FineLine BGA
Notes to
Table
2–14:
(1)
Check the pin table for each DQS/DQ group in the different modes.
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and is used to clock DQ input registers with the DQS
signal.
The Stratix II device has two phase-shifting reference circuits, one on the
top and one on the bottom of the device. The circuit on the top controls
the compensated delay elements for all DQS pins on the top. The circuit
on the bottom controls the compensated delay elements for all DQS pins
on the bottom.
Each phase-shifting reference circuit is driven by a system reference clock,
which must have the same frequency as the DQS signal. Clock pins
CLK[15..12]p feed the phase circuitry on the top of the device and
clock pins CLK[7..4]p feed the phase circuitry on the bottom of the
device. In addition, PLL clock outputs can also feed the phase-shifting
reference circuits.
Figure 2–56
DQS delay shift on the top of the device. This same circuit is duplicated
on the bottom of the device.
2–82
Stratix II Device Handbook, Volume 1
Note (1)
Number of
Number of
×4 Groups
×8/×9 Groups
×16/×18 Groups
8
4
18
8
36
18
36
18
18
8
36
18
36
18
36
18
36
18
illustrates the phase-shift reference circuit control of each
Number of
Number of
×32/×36 Groups
0
0
4
0
8
4
8
4
4
0
8
4
8
4
8
4
8
4
Altera Corporation
May 2007