XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 163

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

DS312-4 (v3.8) August 26, 2009
Introduction
This section describes the various pins on a Spartan®-3E
FPGA and how they connect within the supported compo-
nent packages.
Table 124: Types of Pins on Spartan-3E FPGAs
© 2005–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-
tries. All other trademarks are the property of their respective owners.
DS312-4 (v3.8) August 26, 2009
Product Specification
Color Code
INPUT
Type /
DUAL
VREF
CLK
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired
together to form differential I/Os.
Unrestricted, general-purpose input-only pin. This pin does not have an
output structure, differential termination resistor, or PCI clamp diode.
Dual-purpose pin used in some configuration modes during the
configuration process and then usually available as a user I/O after
configuration. If the pin is not used during configuration, this pin behaves
as an I/O-type pin. Some of the dual-purpose pins are also shared with
bottom-edge global (GCLK) or right-half (RHCLK) clock inputs. See the
Configuration
signals.
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along
with all other VREF pins in the same bank, provides a reference voltage
input for certain I/O standards. If used for a reference voltage within a bank,
all VREF pins within the bank must be connected.
Either a user-I/O pin or Input-only pin, or an input to a specific clock buffer
driver. Every package has 16 global clock inputs that optionally clock the
entire device. The RHCLK inputs optionally clock the right-half of the
device. The LHCLK inputs optionally clock the left-half of the device. Some
of the clock pins are shared with the dual-purpose configuration pins and
are considered DUAL-type. See the
Module 2 for additional information on these signals.
R
section in Module 2 for additional information on these
Description
Clocking Infrastructure
233
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Spartan-3E FPGA Family:
Pinout Descriptions
Product Specification
Pin Types
Most pins on a Spartan-3E FPGA are general-purpose,
user-defined I/O pins. There are, however, up to 11 different
functional types of pins on Spartan-3E packages, as out-
lined in
low, the individual pins are color-coded according to pin
type as in the table.
Table
124. In the package footprint drawings that fol-
section in
IO
IO_Lxxy_#
IP
IP_Lxxy_#
M[2:0]
HSWAP
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
CSO_B
RDWR_B
BUSY/DOUT
INIT_B
A[23:20]
A19/VS2
A18/VS1
A17/VS0
A[16:0]
LDC[2:0]
HDC
IP/VREF_#
IP_Lxxy_#/VREF_#
IO/VREF_#
IO_Lxxy_#/VREF_#
IO_Lxxy_#/GCLK[15:10, 7:2]
IP_Lxxy_#/GCLK[9:8, 1:0]
IO_Lxxy_#/LHCLK[7:0]
IO_Lxxy_#/RHCLK[7:0]
Pin Name(s) in Type
163