XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 18

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Functional Description
V
ers the On-Chip Differential Termination. V
2.5V when using the On-Chip Differential Termination. The
V
To further understand how to combine multiple IOSTAN-
DARDs within a bank, refer to
page
On-Chip Differential Termination
Spartan-3E devices provide an on-chip ~120Ω differential
termination across the input differential receiver terminals.
The on-chip input differential termination in Spartan-3E
devices potentially eliminates the external 100Ω termination
resistor commonly found in differential receiver circuits. Dif-
ferential termination is used for LVDS, mini-LVDS, and
RSDS as applications permit.
On-chip Differential Termination is available in banks with
V
Set the DIFF_TERM attribute to TRUE to enable Differential
Termination on a differential I/O pin pair.
The DIFF_TERM attribute uses the following syntax in the
UCF file:
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors inside each IOB optionally
force a floating I/O or Input-only pin to a determined state.
Pull-up and pull-down resistors are commonly applied to
unused I/Os, inputs, and three-state outputs, but can be
used on any I/O or Input-only pin. The pull-up resistor con-
nects an IOB to V
value depends on the V
ing Characteristics
pull-down resistor similarly connects an IOB to ground with
a resistor. The PULLUP and PULLDOWN attributes and
library primitives turn on these optional resistors.
18
CCO
REF
CCO
Spartan-3E
Differential
Spartan-3E
Differential
INST <I/O_BUFFER_INSTANTIATION_NAME>
DIFF_TERM = “<TRUE/FALSE>”;
Output
Output
19.
lines are not required for differential operation.
provides current to the outputs and additionally pow-
= 2.5V and is not supported on dedicated input pins.
Figure 11: Differential Inputs and Outputs
CCO
in Module 3 for the specifications). The
through a resistor. The resistance
CCO
Z 0 = 50Ω
Z 0 = 50Ω
Z 0 = 50Ω
Z 0 = 50Ω
voltage (see
IOBs Organized into Banks,
DC and Switch-
Differential Input
Differential Input
with On-Chip
CCO
Spartan-3E
Spartan-3E
Differential
Terminator
DS312-2_24_082605
must be
www.xilinx.com
By default, PULLDOWN resistors terminate all unused I/O
and Input-only pins. Unused I/O and Input-only pins can
alternatively be set to PULLUP or FLOAT. To change the
unused I/O Pad setting, set the Bitstream Generator (Bit-
Gen) option
FLOAT. The UnusedPin option is accessed through the
Properties for Generate Programming File in ISE. See
stream Generator (BitGen)
During configuration a Low logic level on the HSWAP pin
activates pull-up resistors on all I/O and Input-only pins not
actively used in the selected configuration mode.
Keeper Circuit
Each I/O has an optional keeper circuit (see
keeps bus lines from floating when not being actively driven.
The KEEPER circuit retains the last logic level on a line after
all drivers have been turned off. Apply the KEEPER
attribute or use the KEEPER library primitive to use the
KEEPER circuitry. Pull-up and pull-down resistors override
the KEEPER settings.
Slew Rate Control and Drive Strength
Each IOB has a slew-rate control that sets the output
switching edge-rate for LVCMOS and LVTTL outputs. The
SLEW attribute controls the slew rate and can either be set
to SLOW (default) or FAST.
Each LVCMOS and LVTTL output additionally supports up
to six different drive current strengths as shown in
To adjust the drive strength for each output, the DRIVE
attribute is set to the desired drive strength: 2, 4, 6, 8, 12,
and 16. Unless otherwise specified in the FPGA application,
the software default IOSTANDARD is LVCMOS25, SLOW
slew rate, and 12 mA output drive.
Table 8: Programmable Output Drive Current
LVTTL
LVCMOS33
IOSTANDARD
Output Path
Input Path
UnusedPin
Figure 12: Keeper Circuit
2
Output Drive Current (mA)
4
Keeper
to PULLUP, PULLDOWN, or
Options.
DS312-2 (v3.8) August 26, 2009
6
Product Specification
Pull-up
Pull-down
8
DS312-2_25_020807
Figure
12
Table
12) that
16
Bit-
8.
R