XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 184

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Pinout Descriptions
User I/Os by Bank
Table 138
user-I/O pins are distributed between the four I/O banks on
the TQ144 package.
Table 138: User I/Os Per Bank for the XC3S100E in the TQ144 Package
Table 139: User I/Os Per Bank for the XC3S250E in TQ144 Package
Footprint Migration Differences
Table 140
ences between the XC3S100E and the XC3S250E FPGAs
that may affect easy migration between devices. There are
four such pins. All other pins not listed in
ditionally migrate between Spartan-3E devices available in
the TQ144 package.
Table 140: TQ144 Footprint Migration Differences
184
Notes:
1.
2.
Notes:
1.
2.
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Package
Package
TQ144 Pin
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Edge
Edge
P10
P29
P31
P66
DIFFERENCES
summarizes any footprint and functionality differ-
and
Table 139
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be
possible depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be
possible depending on how the pin is configured for the device on the left.
I/O Bank
I/O Bank
Bank
0
1
2
3
0
1
2
3
3
3
3
2
indicate how the 108 available
I/O
I/O
VREF(INPUT)
VREF(INPUT)
Maximum
Maximum
108
108
I/O
I/O
26
28
26
28
26
28
26
28
Table 140
XC3S100E Type
uncon-
I/O
I/O
11
20
13
22
9
0
0
9
0
0
www.xilinx.com
The arrows indicate the direction for easy migration. For
example, a left-facing arrow indicates that the pin on the
XC3S250E unconditionally migrates to the pin on the
XC3S100E. It may be possible to migrate the opposite
direction depending on the I/O configuration. For example,
an I/O pin (Type = I/O) can migrate to an input-only pin
(Type = INPUT) if the I/O pin is configured as an input.
INPUT
INPUT
21
19
6
5
4
6
6
5
4
4
All Possible I/O Pins by Type
All Possible I/O Pins by Type
Migration
4
DUAL
DUAL
21
20
42
21
20
42
1
0
1
0
DS312-4 (v3.8) August 26, 2009
VREF
VREF
2
2
2
3
9
2
2
2
3
9
XC3S250E Type
(1)
Product Specification
(1)
VREF(I/O)
VREF(I/O)
INPUT
INPUT
CLK
CLK
0
0
0
0
16
16
8
8
(2)
(2)
8
8
(1)
(1)
(1)
(1)
R