XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 215

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

FG320 Footprint
DS312-4 (v3.8) August 26, 2009
Product Specification
102-
120
47-
48
18
2
I/O: Unrestricted,
general-purpose user I/O
INPUT: Unrestricted,
general-purpose input pin
CONFIG: Dedicated
configuration pins
N.C.: Not connected. Only the
XC3S500E has these pins
( ).
A
B
C
D
G
H
K
M
N
R
U
E
F
J
L
P
T
V
PROG_B
LHCLK2
VCCO_3
INPUT
INPUT
INPUT
INPUT
INPUT
R
L01P_3
L02P_3
L03N_3
L05P_3
L10N_3
L12P_3
L15P_3
L21N_3
L24N_3
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
VCCAUX
VCCAUX
VREF_3
LHCLK3
L01N_3
L02N_3
L05N_3
L12N_3
INPUT
L15N_3
INPUT
L23N_3
INPUT
L03P_3
L10P_3
L21P_3
L24P_3
IRDY2
GND
GND
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
VCCO_3
VCCO_3
LHCLK4
INPUT
L25N_0
HSWAP
L25P_0
INPUT
L04N_3
L06P_3
L09N_3
L13P_3
L16P_3
L18N_3
L22P_3
L23P_3
L01N_2
L01P_2
INPUT
L02N_2
TRDY2
CSO_B
INIT_B
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
INPUT
VREF_3
LHCLK1
LHCLK5
INPUT
VREF_3
INPUT
L24P_0
L24N_0
L04P_3
L06N_3
L09P_3
L11N_3
L13N_3
L16N_3
L18P_3
L20P_3
L22N_3
L03N_2
L03P_2
L02P_2
CSI_B
DOUT
MOSI
BUSY
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4
VCCINT
VCCINT
VREF_0
LHCLK0
LHCLK7
VREF_3
VREF_2
INPUT
INPUT
INPUT
L22P_0
L22N_0
L23P_0
L23N_0
L07N_3
L08N_3
L11P_3
L14N_3
L17N_3
L19P_3
L20N_3
L04P_2
L04N_2
L06P_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5
Figure 87: FG320 Package Footprint (top view)
VCCINT
VCCINT
VCCO_0
VCCO_2
VREF_3
LHCLK6
VREF_2
L20N_0
L21N_0
INPUT
L19N_3
L05N_2
INPUT
L06N_2
L20P_0
L21P_0
L07P_3
L08P_3
L14P_3
L17P_3
L05P_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
46
16
28
4
VCCAUX
VCCO_3
VCCO_3
VCCAUX
VREF_0
VREF_0
INPUT
L18P_0
L18N_0
L19N_0
L19P_0
INPUT
INPUT
L07P_2
L07N_2
INPUT
L08N_2
INPUT
L08P_2
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
DUAL: Configuration pin, then
possible user-I/O
CLK: User I/O, input, or global
buffer input
JTAG: Dedicated JTAG port
pins
GND: Ground
VCCO_0
VCCO_2
INPUT
INPUT
INPUT
INPUT
INPUT
VREF_2
L13P_0
L16P_0
L16N_0
L17P_0
L17N_0
L09N_2
L09P_2
L10P_2
L10N_2
L11P_2
L11N_2
GCLK8
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
www.xilinx.com
Bank 2
VCCO_0
GCLK10
GCLK11
GCLK13
GCLK12
GCLK14
GCLK15
INPUT
L13N_0
GCLK9
L14P_0
L14N_0
L15P_0
L15N_0
L12N_2
L12P_2
L13P_2
L13N_2
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D6
D7
D5
D4
D3
Bank 0
9
RDWR_B
VCCO_2
L12N_0
L11N_0
INPUT
INPUT
L10N_0
L16N_2
L15N_2
INPUT
L14N_2
INPUT
GCLK7
L12P_0
GCLK6
L11P_0
GCLK4
GCLK5
L10P_0
L16P_2
GCLK3
L15P_2
GCLK2
GCLK1
L14P_2
GCLK0
GND
GND
GND
DIN
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M0
D0
D1
D2
M2
VCCO_0
VCCO_2
VREF_0
L09P_0
L09N_0
L08P_0
L08N_0
L18N_2
L18P_2
INPUT
L17P_2
INPUT
L17N_2
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
11
M1
VCCAUX
VCCAUX
VCCO_1
RHCLK1
VCCO_1
INPUT
INPUT
L07P_0
L07N_0
L06N_0
L06P_0
L15P_1
L11N_1
L21P_2
L21N_2
L20N_2
L20P_2
L19P_2
GND
GND
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A2
A9
VCCINT
VCCINT
VREF_0
VCCO_0
RHCLK0
VREF_1
VCCO_2
VREF_2
INPUT
INPUT
INPUT
INPUT
L05P_0
L05N_0
L20N_1
L15N_1
L11P_1
L05N_1
L22P_2
L22N_2
L19N_2
A10
A23
A22
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A1
20-
VCCINT
VCCINT
21
20
VREF_0
RHCLK7
RHCLK3
L04N_0
L03N_0
L21N_1
L14N_1
L12N_1
TRDY1
INPUT
L04N_1
L24N_2
INPUT
L23N_2
INPUT
L04P_0
L03P_0
L20P_1
L17P_1
L05P_1
L24P_2
L23P_2
8
8
A20
A21
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A3
A7
RHCLK6
RHCLK2
VREF_2
INPUT
L02N_0
INPUT
L02P_0
INPUT
L22P_1
L21P_1
L18P_1
L17N_1
L14P_1
L12P_1
L09N_1
L07P_1
L04P_1
INPUT
L03P_1
L25N_2
L25P_2
TMS
VREF: User I/O or input
voltage reference for bank
VCCO: Output voltage supply
for bank
VCCINT: Internal core supply
voltage (+1.2V)
VCCAUX: Auxiliary supply
voltage (+2.5V)
VS1
VS2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A11
I/O
I/O
I/O
I/O
I/O
A18
I/O
A19
15
A4
A8
4
VCCO_1
RHCLK5
VCCO_1
VREF_1
INPUT
L01N_0
L01P_0
L23N_1
L22N_1
L18N_1
L16P_1
L13N_1
L09P_1
L07N_1
L03N_1
L26P_2
L26N_2
LDC0
GND
CCLK
TDO
A12
VS0
A17
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A5
Pinout Descriptions
VCCAUX
VCCAUX
RHCLK4
VREF_1
INPUT
INPUT
INPUT
INPUT
L24N_1
L23P_1
L19N_1
L16N_1
L13P
L10N_1
L06P_1
L01N_1
DONE
GND
LDC2
IRDY1
GND
TCK
HDC
A15
17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A6
A0
_1
DS312-4_06_022106
VCCO_1
VREF_1
VREF_1
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
L08N_1
L06N_1
L02N_1
L24P_1
L19P_1
L10P_1
L08P_1
L02P_1
L01P_1
GND
LDC1
GND
A14
A13
A16
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
215