XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 216

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Pinout Descriptions
FG400: 400-ball Fine-pitch Ball Grid Array
The 400-ball fine-pitch ball grid array, FG400, supports two
different Spartan-3E FPGAs, including the XC3S1200E and
the XC3S1600E. Both devices share a common footprint for
this package as shown in
Table 152
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at:
http://www.xilinx.com/support/documentation/data_sheets/s3e_pin.zip
Pinout Table
Table 152: FG400 Package Pinout
216
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
lists all the FG400 package pins. They are sorted
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L09N_0/VREF_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
XC3S1200E
XC3S1600E
Pin Name
Table 152
and
FG400
Figure
Ball
C10
C11
C17
C14
D14
C13
A12
E13
E16
F13
F14
B17
A18
A19
A17
A16
A15
B15
A13
A14
B13
C7
G7
A3
A8
E8
88.
VREF
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 152: FG400 Package Pinout (Continued)
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L15N_0/GCLK5
IO_L15P_0/GCLK4
IO_L16N_0/GCLK7
IO_L16P_0/GCLK6
IO_L18N_0/GCLK11
IO_L18P_0/GCLK10
IO_L19N_0
IO_L19P_0
IO_L21N_0
IO_L21P_0
IO_L22N_0/VREF_0
IO_L22P_0
IO_L24N_0/VREF_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L30N_0/VREF_0
IO_L30P_0
IO_L31N_0
IO_L31P_0
IO_L32N_0/HSWAP
IO_L32P_0
IP
IP
IP_L02N_0
IP_L02P_0
IP_L05N_0
IP_L05P_0
IP_L08N_0
IP_L08P_0
IP_L11N_0
XC3S1200E
XC3S1600E
Pin Name
DS312-4 (v3.8) August 26, 2009
Product Specification
FG400
Ball
G11
C16
D16
D15
C15
G14
C12
D12
E12
F12
F11
E10
E11
A10
B18
E14
E15
C9
D6
C5
D4
A9
F9
E9
D9
B8
B9
F7
F8
A6
A7
B5
B6
C6
D5
A2
B2
C4
E5
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
VREF
VREF
DUAL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R