XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 5

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Configuration
Spartan-3E FPGAs are programmed by loading configura-
tion data into robust, reprogrammable, static CMOS config-
uration latches (CCLs) that collectively control all functional
elements and routing resources. The FPGA’s configuration
data is stored externally in a PROM or some other non-vol-
atile medium, either on or off the board. After applying
power, the configuration data is written to the FPGA using
any of seven different modes:
•
•
•
•
•
•
Furthermore, Spartan-3E FPGAs support MultiBoot config-
uration, allowing two or more FPGA configuration bit-
streams to be stored in a single parallel NOR Flash. The
FPGA application controls which configuration to load next
and when to load it.
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
DS312-1 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
3.
Device
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Size (mm)
Package
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
All Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4:
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins.
The XC3S500E is available in the VQG100 Pb-free package and not the standard VQ100. The VQG100 and VQ100 pin-outs are identical
and general references to the VQ100 will apply to the XC3S500E.
R
User
66
(7)
(7)
(7)
66
66
VQG100
-
-
16 x 16
(3)
VQ100
Diff
30
(2)
30
(2)
30
(2)
-
-
User
(11)
(7)
(7)
83
92
92
CPG132
-
-
CP132
8 x 8
Diff
(2)
(2)
(2)
35
41
41
-
-
User
108
(28)
108
(28)
TQG144
-
-
-
22 x 22
TQ144
Diff
(4)
(4)
40
40
-
-
-
www.xilinx.com
User
(32)
(32)
158
158
PQG208
-
-
-
28 x 28
PQ208
I/O Capabilities
The Spartan-3E FPGA SelectIO interface supports many
popular single-ended and differential standards.
shows the number of user I/Os as well as the number of dif-
ferential I/O pairs available for each device/package combi-
nation.
Spartan-3E FPGAs support the following single-ended
standards:
•
•
•
•
•
Spartan-3E FPGAs support the following differential stan-
dards:
•
•
•
•
•
•
•
Diff
65
(5)
65
(5)
-
-
-
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3V PCI at 33 MHz, and in some devices,
HSTL I and III at 1.8V, commonly used in memory
applications
SSTL I at 1.8V and 2.5V, commonly used for memory
applications
LVDS
Bus LVDS
mini-LVDS
RSDS
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, Type I)
2.5V LVPECL inputs
User
(40)
(41)
(40)
172
190
190
FTG256
-
-
17 x 17
FT256
Diff
(8)
(8)
(8)
68
77
77
-
-
User
232
(56)
250
(56)
250
(56)
FGG320
-
-
19 x 19
FG320
(12)
(12)
(12)
Diff
92
99
99
-
-
Pinout
User
(72)
(72)
304
304
FGG400
-
-
-
21 x 21
FG400
Descriptions.
Diff
124
(20)
124
(20)
-
-
-
66 MHz
User
(82)
376
FGG484
-
-
-
-
FG484
23 x 23
Table 2
(21)
Diff
156
-
-
-
-
5