XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 59

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Clocking Infrastructure
For additional information, refer to the Using Global Clock
Resources chapter in UG331.
The Spartan-3E clocking infrastructure, shown in
provides a series of low-capacitance, low-skew interconnect
lines well-suited to carrying high-frequency signals through-
out the FPGA. The infrastructure also includes the clock
inputs and BUFGMUX clock buffers/multiplexers. The Xilinx
Place-and-Route (PAR) software automatically routes
high-fanout clock signals using these resources.
Clock Inputs
Clock pins accept external clock signals and connect
directly to DCMs and BUFGMUX elements. Each Spar-
tan-3E FPGA has:
•
•
•
Clock inputs optionally connect directly to DCMs using ded-
icated connections.
the clock inputs that best feed a specific DCM within a given
Spartan-3E part number. Different Spartan-3E FPGA densi-
ties have different numbers of DCMs. The XC3S1200E and
XC3S1600E are the only two densities with the left- and
right-edge DCMs.
Each clock input is also optionally a user-I/O pin and con-
nects to internal interconnect. Some clock pad pins are
input-only pins as indicated in
ule 4).
Design Note
Avoid using global clock input GCLK1 as it is always shared
with the M2 mode select pin. Global clock inputs GCLK0,
GCLK2, GCLK3, GCLK12, GCLK13, GCLK14, and
GCLK15 have shared functionality in some configuration
modes.
DS312-2 (v3.8) August 26, 2009
Product Specification
16 Global Clock inputs (GCLK0 through GCLK15)
located along the top and bottom edges of the FPGA
8 Right-Half Clock inputs (RHCLK0 through RHCLK7)
located along the right edge
8 Left-Half Clock inputs (LHCLK0 through LHCLK7)
located along the left edge
R
Table
30,
Table
Pinout Descriptions
31, and
Table 32
Figure
(Mod-
www.xilinx.com
show
45,
Clock Buffers/Multiplexers
Clock Buffers/Multiplexers either drive clock input signals
directly onto a clock line (BUFG) or optionally provide a mul-
tiplexer to switch between two unrelated, possibly asynchro-
nous clock signals (BUFGMUX).
Each BUFGMUX element, shown in
multiplexer. The select line, S, chooses which of the two
inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
described in
other is glitch-less, and done in such a way that the output
High and Low times are never shorter than the shortest
High or Low time of either input clock. The two clock inputs
can be asynchronous with regard to each other, and the S
input can change at any time, except for a short setup time
prior to the rising edge of the presently selected clock (I0 or
I1). This setup time is specified as TGSI in
page
results in an undefined runt pulse output.
Table 40: BUFGMUX Select Mechanism
The BUFG clock buffer primitive drives a single clock signal
onto the clock network and is essentially the same element
as a BUFGMUX, just without the clock select mechanism.
Similarly, the BUFGCE primitive creates an enabled clock
buffer using the BUFGMUX select mechanism.
The I0 and I1 inputs to an BUFGMUX element originate
from clock input pins, DCMs, or Double-Line interconnect,
as shown in
BUFGMUX elements distributed around the four edges of
the device. Clock signals from the four BUFGMUX elements
at the top edge and the four at the bottom edge are truly glo-
bal and connect to all clocking quadrants. The eight
left-edge BUFGMUX elements only connect to the two clock
quadrants in the left half of the device. Similarly, the eight
right-edge BUFGMUX elements only connect to the right
half of the device.
BUFGMUX elements are organized in pairs and share I0
and I1 connections with adjacent BUFGMUX elements from
a common clock switch matrix as shown in
example, the input on I0 of one BUFGMUX is also a shared
input to I1 of the adjacent BUFGMUX.
The clock switch matrix for the left- and right-edge BUFG-
MUX elements receive signals from any of the three follow-
ing sources: an LHCLK or RHCLK pin as appropriate, a
Double-Line interconnect, or a DCM in the XC3S1200E and
XC3S1600E devices.
140. Violating this setup time requirement possibly
S Input
Figure
Table
0
1
40. The switching from one clock to the
46. As shown in
Functional Description
Figure
Figure
O Output
I0 Input
I1 Input
45, there are 24
46, is a 2-to-1
Figure
Table 101,
46. For
59