XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 69

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Table 46: Pin Behavior during Configuration (Continued)
Table 47: Default I/O Standard Setting During Configuration (VCCO_2 = 2.5V)
The HSWAP pin itself has an pull-up resistor enabled during
configuration. However, the VCCO_0 supply voltage must
be applied before the pull-up resistor becomes active. If the
VCCO_0 supply ramps after the VCCO_2 power supply, do
DS312-2 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
3.
All, including CCLK
Gray shaded cells represent pins that are in a high-impedance state (Hi-Z, floating) during configuration. These pins have an optional
internal pull-up resistor to their respective V
Yellow shaded cells represent pins with an internal pull-up resistor to its respective voltage supply rail that is active during
configuration, regardless of the HSWAP pin.
Note that dual-purpose outputs are supplied by V
Pin Name
RDWR_B
A19/VS2
A18/VS1
A17/VS0
D0/DIN
LDC0
LDC1
LDC2
HDC
A23
A22
A21
A20
A16
A15
A14
A13
A12
A11
A10
D1
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Pin(s)
R
Master Serial
DIN
I/O Standard
LVCMOS25
SPI (Serial
Flash)
VS2
VS1
VS0
DIN
CCO
Output Drive
supply pin that is active throughout configuration if the HSWAP input is Low.
CCO
BPI (Parallel
8 mA
NOR Flash)
RDWR_B
, and configuration inputs are supplied by V
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LDC0
LDC1
LDC2
HDC
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
D1
D0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
not let HSWAP float; tie HSWAP to the desired logic level
externally.
Spartan-3E FPGAs have only six dedicated configuration
pins, including the DONE and PROG_B pins, and the four
JTAG
RDWR_B
Parallel
Slave
D1
D0
Slew Rate
Slow
CCAUX
Slave Serial
.
Functional Description
DIN
I/O Bank
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(3)
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