XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 75

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in
(M[2:0] = <0:0:0>) for the FPGA connected to the Platform
Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for
all other FPGAs in the daisy-chain. After the master
FPGA—the FPGA on the left in the diagram—finishes load-
ing its configuration data from the Platform Flash, the mas-
ter device supplies data using its DOUT output pin to the
next device in the daisy-chain, on the falling CCLK edge.
JTAG Interface
Both the Spartan-3E FPGA and the Platform Flash PROM
have a four-wire IEEE 1149.1/1532 JTAG port. Both devices
share the TCK clock input and the TMS mode select input.
The devices may connect in either order on the JTAG chain
with the TDO output of one device feeding the TDI input of
the following device in the chain. The TDO output of the last
device in the JTAG chain drives the JTAG connector.
The JTAG interface on Spartan-3E FPGAs is powered by
the 2.5V V
supply input must also be 2.5V. To create a 3.3V JTAG inter-
face, please refer to application note XAPP453: The 3.3V
Configuration of Spartan-3 FPGAs for additional informa-
tion.
In-System Programming Support
Both the FPGA and the Platform Flash PROM are in-system
programmable via the JTAG chain. Download support is
DS312-2 (v3.8) August 26, 2009
Product Specification
Recommend
open-drain
PROG_B
driver
TMS
TCK
TDO
TDI
+2.5V
JTAG
Serial Master
CCAUX
R
Mode
‘0’
‘0’
‘0’
P
Figure
supply. Consequently, the PROM’s V
HSWAP
M2
M1
M0
TDI
TMS
TCK
PROG_B
Spartan-3E
VCCINT
52. Use Master Serial mode
FPGA
+1.2V
GND
VCCAUX
VCCO_0
VCCO_2
INIT_B
DOUT
DONE
CCLK
TDO
DIN
Figure 52: Daisy-Chaining from Master Serial Mode
VCCO_0
+2.5V
V
D0
CLK
OE/RESET
CE
CF
TDI
TMS
TCK
www.xilinx.com
Platform Flash
XCFxxS = +3.3V
XCFxxP = +1.8V
CCJ
VCCINT
XCFxx
GND
VCCO
provided by the Xilinx iMPACT programming software and
the associated Xilinx
USB
Storing Additional User Data in Platform Flash
After configuration, the FPGA application can continue to
use the Master Serial interface pins to communicate with
the Platform Flash PROM. If desired, use a larger Platform
Flash PROM to hold additional non-volatile application data,
such as MicroBlaze processor code, or other user data such
as serial numbers and Ethernet MAC IDs. The FPGA first
configures from Platform Flash PROM. Then using FPGA
logic after configuration, the FPGA copies MicroBlaze code
from Platform Flash into external DDR SDRAM for code
execution.
See XAPP694: Reading User Data from Configuration
PROMs and XAPP482: MicroBlaze Platform Flash/PROM
Boot Loader and User Data Storage for specific details on
how to implement such an interface.
SPI Serial Flash Mode
For additional information, refer to the “Master SPI Mode”
chapter in UG332.
In SPI Serial Flash mode (M[2:0] = <0:0:1>), the Spartan-3E
FPGA configures itself from an attached industry-standard
SPI serial Flash PROM, as illustrated in
Figure
its internal oscillator to the clock input of the attached SPI
Flash PROM.
VCCJ
CEO
TDO
programming cables.
+2.5V
+2.5V
54. The FPGA supplies the CCLK output clock from
V
V
Slave
Serial
Mode
P
‘1’
‘1’
‘1’
Parallel Cable IV
HSWAP
M2
M1
M0
CCLK
DIN
TDI
PROG_B
TMS
TCK
Spartan-3E
VCCINT
+1.2V
FPGA
GND
Functional Description
VCCAUX
VCCO_0
VCCO_2
INIT_B
DOUT
DONE
TDO
or
VCCO_0
+2.5V
Platform Cable
V
Figure 53
DS312-2_45_082009
CCLK
DOUT
PROG_B
TCK
TMS
DONE
INIT_B
and
75