XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 91

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

desired, use a larger parallel Flash PROM to contain addi-
tional non-volatile application data, such as MicroBlaze pro-
cessor code, or other user data, such as serial numbers and
Ethernet MAC IDs. In such an example, the FPGA config-
ures from parallel Flash PROM. Then using FPGA logic
after configuration, a MicroBlaze processor embedded
within the FPGA can either execute code directly from par-
allel Flash PROM or copy the code to external DDR
SDRAM and execute from DDR SDRAM. Similarly, the
FPGA application can store non-volatile application data
within the parallel Flash PROM.
The FPGA configuration data is stored starting at either at
location 0 or the top of memory (addresses all ones) or at
both locations for MultiBoot mode. Store any additional data
beginning in other available parallel Flash PROM sectors.
Do not mix configuration data and user data in the same
sector.
Similarly, the parallel Flash PROM interface can be
expanded to additional parallel peripherals.
The address, data, and LDC1 (OE#) and HDC (WE#) con-
trol signals are common to all parallel peripherals. Connect
the chip-select input on each additional peripheral to one of
the FPGA user I/O pins. If HSWAP = 0 during configuration,
the FPGA holds the chip-select line High via an internal
pull-up resistor. If HSWAP = 1, connect the select line to
+3.3V via an external 4.7 kΩ pull-up resistor to avoid spuri-
ous read or write operations. After configuration, drive the
select line Low to select the desired peripheral. Refer to the
individual peripheral data sheet for specific interface and
communication protocol requirements.
The FPGA optionally supports a 16-bit peripheral interface
by driving the LDC2 (BYTE#) control pin High after configu-
ration. See
additional information.
The FPGA provides up to 24 address lines during configu-
ration, addressing up to 128 Mbits (16 Mbytes). If using a
larger parallel PROM, connect the upper address lines to
FPGA user I/O. During configuration, the upper address
lines will be pulled High if HSWAP = 0. Otherwise, use
Table 63: FPGA Connections to Flash PROM with IO15/A-1 Pin
DS312-2 (v3.8) August 26, 2009
Product Specification
LDC2
LDC1
LDC0
HDC
FPGA Pin
Precautions Using x8/x16 Flash PROMs
R
BYTE#
OE#
CS#
WE#
Connection to Flash PROM with
IO15/A-1 Pin
x8 Flash PROM Interface After
Drive LDC2 Low or leave
unconnected and tie PROM
BYTE# input to GND
Active-Low Flash PROM
output-enable control
Active-Low Flash PROM
chip-select control
Flash PROM write-enable
control
www.xilinx.com
for
FPGA Configuration
external pull-up or pull-down resistors on these address
lines to define their values during configuration.
Precautions Using x8/x16 Flash PROMs
only. Many higher-density Flash PROMs support both
byte-wide (x8) and halfword-wide (x16) data paths and
include a mode input called BYTE# that switches between
x8 or x16. During configuration, Spartan-3E FPGAs only
support byte-wide data. However, after configuration, the
FPGA supports either x8 or x16 modes. In x16 mode, up to
eight additional user I/O pins are required for the upper data
bits, D[15:8].
Connecting a Spartan-3E FPGA to a x8/x16 Flash PROM is
simple, but does require a precaution. Various Flash PROM
vendors use slightly different interfaces to support both x8
and x16 modes. Some vendors (Intel, Micron, some STMi-
croelectronics devices) use a straightforward interface with
pin naming that matches the FPGA connections. However,
the PROM’s A0 pin is wasted in x16 applications and a sep-
arate FPGA user-I/O pin is required for the D15 data line.
Fortunately, the FPGA A0 pin is still available as a user I/O
after configuration, even though it connects to the Flash
PROM.
Other vendors (AMD, Atmel, Silicon Storage Technology,
some STMicroelectronics devices) use a pin-efficient inter-
face but change the function of one pin, called IO15/A-1,
depending if the PROM is in x8 or x16 mode. In x8 mode,
BYTE# = 0, this pin is the least-significant address line. The
A0 address line selects the halfword location. The A-1
address line selects the byte location. When in x16 mode,
BYTE# = 1, the IO15/A-1 pin becomes the most-significant
data bit, D15 because byte addressing is not required in this
mode. Check to see if the Flash PROM has a pin named
“IO15/A-1” or “DQ15/A-1”. If so, be careful to connect
x8/x16 Flash PROMs correctly, as shown in
remember that the D[14:8] data connections require FPGA
user I/O pins but that the D15 data is already connected for
the FPGA’s A0 pin.
D
Most low- to mid-density PROMs are byte-wide (x8)
Drive LCD2 High
Active-Low Flash PROM
output-enable control
Active-Low Flash PROM
chip-select control
Flash PROM write-enable control
x16 Flash PROM Interface After
FPGA Configuration
Functional Description
Table
63. Also,
91