IC FPGA 400 CLB'S 160-PQFP

 

XC4010E-3PQ160C

Manufacturer Part NumberXC4010E-3PQ160C
DescriptionIC FPGA 400 CLB'S 160-PQFP
ManufacturerXilinx Inc
SeriesXC4000E/X
XC4010E-3PQ160C datasheets

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Specifications of XC4010E-3PQ160C

Number Of Logic Elements/cells950Number Of Labs/clbs400
Total Ram Bits12800Number Of I /o129
Number Of Gates10000Voltage - Supply4.75 V ~ 5.25 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case160-BQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names122-1103  
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Product Obsolete or Under Obsolescence
XC4000E and XC4000X Series Field Programmable Gate Arrays
8
IOB
IOB
1
I
CLB
CLB
O
B
I
CLB
CLB
O
B
2
IOB
IOB
3
Figure 36: Any BUFGLS (GCK1 - GCK8) Can
Drive Any or All Clock Inputs on the Device
Global Early Buffers
Each corner of the XC4000X device has two Global Early
buffers. The primary purpose of the Global Early buffers is
to provide an earlier clock access than the potentially
heavily-loaded Global Low-Skew buffers. A clock source
applied to both buffers will result in the Global Early clock
edge occurring several nanoseconds earlier than the Glo-
bal Low-Skew buffer clock edge, due to the lighter loading.
Global Early buffers also facilitate the fast capture of device
inputs, using the Fast Capture latches described in
Input Signals” on page
20. For Fast Capture, take a single
clock signal, and route it through both a Global Early buffer
and a Global Low-Skew buffer. (The two buffers share an
input pad.) Use the Global Early buffer to clock the Fast
Capture latch, and the Global Low-Skew buffer to clock the
normal input flip-flop or latch, as shown in
page
23.
The Global Early buffers can also be used to provide a fast
Clock-to-Out on device output pins. However, an early clock
in the output flip-flop IOB must be taken into consideration
when calculating the internal clock speed for the design.
The Global Early buffers at the left and right edges of the
chip have slightly different capabilities than the ones at the
top and bottom. Refer to
Figure
Figure 35 on page 36
while reading the following explana-
tion.
Each Global Early buffer can access the eight vertical Glo-
bal lines for all CLBs in the quadrant. Therefore, only
one-fourth of the CLB clock pins can be accessed. This
restriction is in large part responsible for the faster speed of
the buffers, relative to the Global Low-Skew buffers.
6-38
8
7
1
6
I
I
O
O
B
B
I
I
O
O
B
B
2
5
3
4
X6753
Figure 37: Left and Right BUFGEs Can Drive Any or
All Clock Inputs in Same Quadrant or Edge (GCK1 is
shown. GCK2, GCK5 and GCK6 are similar.)
The left-side Global Early buffers can each drive two of the
four vertical lines accessing the IOBs on the entire left edge
of the device. The right-side Global Early buffers can each
drive two of the eight vertical lines accessing the IOBs on
the entire right edge of the device. (See
Each left and right Global Early buffer can also drive half of
the IOBs along either the top or bottom edge of the device,
using a dedicated line that can only be accessed through
the Global Early buffers.
“IOB
The top and bottom Global Early buffers can drive half of
the IOBs along either the left or right edge of the device, as
shown in
Figure
tom IOBs via the CLB global lines.
Figure 17 on
8
1
I
O
B
37,
Figure
38, and
I
O
B
2
3
Figure 38: Top and Bottom BUFGEs Can Drive Any
or All Clock Inputs in Same Quadrant (GCK8 is
shown. GCK3, GCK4 and GCK7 are similar.)
7
IOB
IOB
6
I
CLB
CLB
O
B
I
CLB
CLB
O
B
5
IOB
IOB
4
X6751
Figure
37.)
38. They can only access the top and bot-
7
IOB
IOB
6
I
CLB
CLB
O
B
I
CLB
CLB
O
B
5
IOB
IOB
4
X6747
May 14, 1999 (Version 1.6)
R

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