IC FPGA 400 CLB'S 160-PQFP

 

XC4010E-3PQ160C

Manufacturer Part NumberXC4010E-3PQ160C
DescriptionIC FPGA 400 CLB'S 160-PQFP
ManufacturerXilinx Inc
SeriesXC4000E/X
XC4010E-3PQ160C datasheets

Availability: In stock

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

Select quantity

 

Specifications of XC4010E-3PQ160C

Number Of Logic Elements/cells950Number Of Labs/clbs400
Total Ram Bits12800Number Of I /o129
Number Of Gates10000Voltage - Supply4.75 V ~ 5.25 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case160-BQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names122-1103  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Page 41/68

Download datasheet (983Kb)Embed
PrevNext
Product Obsolete or Under Obsolescence
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 17: Boundary Scan Instructions
Instruction I2
Test
TDO Source
I1
I0
Selected
0
0
0
EXTEST
DR
0
0
1
SAMPLE/PR
DR
ELOAD
0
1
0
USER 1
BSCAN.
TDO1
0
1
1
USER 2
BSCAN.
TDO2
1
0
0
READBACK
Readback
Data
1
0
1
CONFIGURE
DOUT
1
1
0
Reserved
—
1
1
1
BYPASS
Bypass
Register
TDO.T
Bit 0 ( TDO end)
TDO.O
Bit 1
Bit 2
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MD1.T
MD1.O
MD1.I
MD0.I
MD2.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
B SCANT.UPD
(TDI end)
Figure 42:
Boundary Scan Bit Sequence
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant dur-
ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
To prevent activation of boundary scan during configura-
tion, do either of the following:
• TMS: Tie High to put the Test Access Port controller
in a benign RESET state
• TCK: Tie High or Low—don't toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017.001, “ Boundary Scan in
XC4000E Devices .“
May 14, 1999 (Version 1.6)
Optional
I/O Data
Source
DR
TDI
Pin/Logic
TMS
TCK
User Logic
From
User Logic
User Logic
Figure 43: Boundary Scan Schematic Example
Pin/Logic
Configuration
Disabled
Configuration is the process of loading design-specific pro-
—
gramming data into one or more FPGAs to define the func-
—
tional
operation
of
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip. XC4000
Series devices use several hundred bits of configuration
data per CLB and its associated interconnects. Each con-
figuration bit defines the state of a static memory cell that
controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The XACT step
development system translates the design into a netlist file.
It automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
Special Purpose Pins
Three configuration mode pins (M2, M1, M0) are sampled
prior to configuration to determine the configuration mode.
After configuration, these pins can be used as auxiliary
connections. M2 and M0 can be used as inputs, and M1
can be used as an output. The XACT step development sys-
X6075
tem does not use these resources unless they are explicitly
specified in the design entry. This is done by placing a spe-
cial pad symbol called MD2, MD1, or MD0 instead of the
input or output pad symbol.
In XC4000 Series devices, the mode pins have weak
pull-up resistors during configuration. With all three mode
pins High, Slave Serial mode is selected, which is the most
popular configuration mode. Therefore, for the most com-
mon configuration mode, the mode pins can be left uncon-
nected. (Note, however, that the internal pull-up resistor
value can be as high as 100 k .) After configuration, these
pins can individually have weak pull-up or pull-down resis-
tors, as specified in the design. A pull-down resistor value
of 4.7 k is recommended.
These pins are located in the lower left chip corner and are
near the readback nets. This location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of M0/RT, M1/RD is desired.
To User
Logic
IBUF
BSCAN
TDO
TDI
TDO
TMS
DRCK
TCK
IDLE
To User
Logic
TDO1
SEL1
TDO2
SEL2
X2675
the
internal
blocks
and
their
6-45
6

Related parts for XC4010E-3PQ160C

Part Number DescriptionManufacturer Datasheet
  XC4010E-3PQ160I IC FPGA I-TEMP 5V 3SPD 160-PQFP - XC4010E-3PQ160I Xilinx Inc
  XC4010-5PQ208C IC LOGIC CL ARRAY 10K GAT 208PQ Xilinx Inc
  XC4010D-5PQ160C IC LOGIC CL ARRAY 10K GAT 160PQ Xilinx Inc
  XC4010E-3PC84C IC FPGA 400 CLB'S 84-PLCC Xilinx Inc
  XC4010E-4PC84C IC FPGA 400 CLB'S 84-PLCC Xilinx Inc
  XC4010E-4PQ160C IC FPGA 400 CLB'S 160-PQFP Xilinx Inc
XC4010E-2PQ208C  XC4010E-2PQ208C IC FPGA 400 CLB'S 208-PQFP Xilinx Inc
XC4010E-3PQ208C  XC4010E-3PQ208C IC FPGA 400 CLB'S 208-PQFP Xilinx Inc
XC4010E-4PQ208C  XC4010E-4PQ208C IC FPGA 400 CLB'S 208-PQFP Xilinx Inc
  XC4010L-5PQ208C IC 3.3V FPGA 400 CLB'S 208-PQFP Xilinx Inc
  XC4010E-1BG225C IC FPGA C-TEMP 5V 1SPD 225-PBGA Xilinx Inc
  XC4010E-1HQ208C IC FPGA C-TEMP 5V 1SPD 208-HQFP Xilinx Inc
  XC4010E-1PC84C IC FPGA C-TEMP 5V 1SPD 84-PLCC Xilinx Inc
  XC4010E-1PG191C IC FPGA C-TEMP 5V 1SPD 191-CPGA Xilinx Inc
  XC4010E-1PQ160C IC FPGA C-TEMP 5V 1SPD 160-PQFP Xilinx Inc