Product Obsolete or Under Obsolescence
XC4000E and XC4000X Series Field Programmable Gate Arrays
Low. During this time delay, or as long as the PROGRAM
input is asserted, the conﬁguration logic is held in a Conﬁg-
uration Memory Clear state. The conﬁguration-memory
frames are consecutively initialized, using the internal oscil-
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the conﬁgura-
tion frames and then tests the INIT input.
During initialization and conﬁguration, user pins HDC, LDC,
INIT and DONE provide status outputs for the system inter-
face. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of power.
The open drain INIT pin is released after the ﬁnal initializa-
tion pass through the frame addresses. There is a deliber-
ate delay of 50 to 250 s (up to 10% longer for low-voltage
devices) before a Master-mode device recognizes an inac-
tive INIT. Two internal clocks after the INIT pin is recognized
as High, the FPGA samples the three mode lines to deter-
mine the conﬁguration mode. The appropriate interface
lines become active and the conﬁguration preamble and
data can be loaded.Conﬁguration
The 0010 preamble code indicates that the following 24 bits
represent the length count. The length count is the total
number of conﬁguration clocks needed to load the com-
plete conﬁguration data. (Four additional conﬁguration
clocks are required to complete the conﬁguration process,
as discussed below.) After the preamble and the length
count have been passed through to all devices in the daisy
chain, DOUT is held High to prevent frame start bits from
reaching any daisy-chained devices.
A speciﬁc conﬁguration bit, early in the ﬁrst frame of a mas-
ter device, controls the conﬁguration-clock rate and can
increase it by a factor of eight. Therefore, if a fast conﬁgu-
ration clock is selected by the bitstream, the slower clock
rate is used until this conﬁguration bit is detected.
Each frame has a start ﬁeld followed by the frame-conﬁgu-
ration data bits and a frame error ﬁeld. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all conﬁgura-
tion frames have been loaded into an FPGA, DOUT again
follows the input data so that the remaining data is passed
on to the next device.
Delaying Conﬁguration After Power-Up
There are two methods of delaying conﬁguration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See
Figure 46 on page
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
May 14, 1999 (Version 1.6)
rise time is excessive or poorly deﬁned. As long as PRO-
GRAM is Low, the FPGA keeps clearing its conﬁguration
memory. When PROGRAM goes High, the conﬁguration
memory is cleared one more time, followed by the begin-
ning of conﬁguration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output. The XC4000
Series PROGRAM pin has a permanent weak pull-up.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of conﬁguration causes the
FPGA to wait after completing the conﬁguration memory
clear operation. When INIT is no longer held Low exter-
nally, the device determines its conﬁguration mode by cap-
turing its mode pins, and is ready to start the conﬁguration
process. A master device waits up to an additional 250 s
to make sure that any slaves in the optional daisy chain
have seen that INIT is High.
Start-up is the transition from the conﬁguration process to
the intended user operation. This transition involves a
change from one clock source to another, and a change
from interfacing parallel or serial conﬁguration data where
most outputs are 3-stated, to normal operation with I/O pins
active in the user-system. Start-up must make sure that the
user-logic ‘wakes up’ gracefully, that the outputs become
active without causing contention with the conﬁguration sig-
nals, and that the internal ﬂip-ﬂops are released from the
global Reset or Set at the right time.
describes start-up timing for the three Xilinx fam-
ilies in detail. The conﬁguration modes can use any of the
four timing sequences.
To access the internal start-up signals, place the STARTUP
Different FPGA families have different start-up sequences.
The XC2000 family goes through a ﬁxed sequence. DONE
goes High and the internal global Reset is de-activated one
CCLK period after the I/O become active.
The XC3000A family offers some ﬂexibility. DONE can be
programmed to go High one CCLK period before or after
the I/O become active. Independent of DONE, the internal
global Reset is de-activated one CCLK period before or
after the I/O become active.
The XC4000 Series offers additional ﬂexibility. The three
events — DONE going High, the internal Set/Reset being
de-activated, and the user I/O going active — can all occur
in any arbitrary sequence. Each of them can occur one
CCLK period before or after, or simultaneous with, any of
the others. This relative timing is selected by means of soft-
ware options in the bitstream generation software.