XC4010E-3PQ160C | |
|---|---|
| Manufacturer Part Number | XC4010E-3PQ160C |
| Description | IC FPGA 400 CLB'S 160-PQFP |
| Manufacturer | Xilinx Inc |
| Series | XC4000E/X |
| XC4010E-3PQ160C datasheets |
|
Availability: In stock
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Warranty: 60 days
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Specifications of XC4010E-3PQ160C | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 950 | Number Of Labs/clbs | 400 |
| Total Ram Bits | 12800 | Number Of I /o | 129 |
| Number Of Gates | 10000 | Voltage - Supply | 4.75 V ~ 5.25 V |
| Mounting Type | Surface Mount | Operating Temperature | 0°C ~ 85°C |
| Package / Case | 160-BQFP | Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant |
| Other names | 122-1103 | ||
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PrevNext
Product Obsolete or Under Obsolescence
XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C 1 • • • C 4
G 4
G 3
LOGIC
FUNCTION
G'
OF
G 2
G1-G4
G 1
F 4
F 3
LOGIC
FUNCTION
F'
OF
F 2
F1-F4
F 1
K
(CLOCK)
Figure 1: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)
Flip-Flops
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in one or two flip-flops, and
connect their outputs to the interconnect network as well.
The two edge-triggered D-type flip-flops have common
clock (K) and clock enable (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in
Table
2.
Latches (XC4000X only)
The CLB storage elements can also be configured as
latches. The two latches have common clock (K) and clock
enable (EC) inputs. Storage element functionality is
described in
Table
2.
Clock Input
Each flip-flop can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage ele-
ments. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
6-10
H 1
D IN /H 2
SR/H 0
DIN
F'
G'
H'
LOGIC
FUNCTION
G'
OF
H'
H'
F', G',
AND
H1
DIN
F'
G'
H'
H'
F'
Multiplexer Controlled
by Configuration Program
Clock Enable
The clock enable signal (EC) is active High. The EC pin is
shared by both storage elements. If left unconnected for
either, the clock enable for that storage element defaults to
the active state. EC is not invertible within the CLB.
Table 2: CLB Storage Element Functionality
(active rising edge is shown)
Mode
Power-Up or
GSR
Flip-Flop
Latch
Both
Legend:
X
__/
SR
0*
1*
EC
S/R
Bypass
CONTROL
YQ
SD
D
Q
EC
RD
1
Y
Bypass
S/R
CONTROL
XQ
SD
D
Q
EC
RD
1
X
X6692
K
EC
SR
D
X
X
X
X
X
X
1
X
__/
1*
0*
D
0
X
0*
X
1
1*
0*
X
0
1*
0*
D
X
0
0*
X
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
May 14, 1999 (Version 1.6)
R
Q
SR
SR
D
Q
Q
D
Q
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