IC APEX 20KE FPGA 100K 208-PQFP

 

EP20K100EQC208-3

Manufacturer Part NumberEP20K100EQC208-3
DescriptionIC APEX 20KE FPGA 100K 208-PQFP
ManufacturerAltera
SeriesAPEX-20K®
EP20K100EQC208-3 datasheets

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Specifications of EP20K100EQC208-3

Number Of Logic Elements/cells4160Number Of Labs/clbs416
Total Ram Bits53248Number Of I /o151
Number Of Gates263000Voltage - Supply1.71 V ~ 1.89 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case208-MQFP, 208-PQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-2092  
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APEX 20K Programmable Logic Device Family Data Sheet
48
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to CLK2p.
combinations supported by the ClockLock and ClockBoost circuitry. The
CLK2p pin can feed both the ClockLock and ClockBoost circuitry in the
APEX 20K device. However, when both circuits are used, the other clock
pin (
) cannot be used.
CLK1p
Table 14. Multiplication Factor Combinations
Clock 1
×1
×1, ×2
×1, ×2, ×4
APEX 20KE ClockLock Feature
APEX 20KE devices include an enhanced ClockLock feature set. These
devices include up to four PLLs, which can be used independently. Two
PLLs are designed for either general-purpose use or LVDS use (on devices
that support LVDS I/O pins). The remaining two PLLs are designed for
general-purpose use. The EP20K200E and smaller devices have two PLLs;
the EP20K300E and larger devices have four PLLs.
The following sections describe some of the features offered by the
APEX 20KE PLLs.
External PLL Feedback
The ClockLock circuit’s output can be driven off-chip to clock other
devices in the system; further, the feedback loop of the PLL can be routed
off-chip. This feature allows the designer to exercise fine control over the
I/O interface between the APEX 20KE device and another high-speed
device, such as SDRAM.
Clock Multiplication
The APEX 20KE ClockBoost circuit can multiply or divide clocks by a
programmable number. The clock can be multiplied by m/(n × k) or
m/(n × v), where m and k range from 2 to 160, and n and v range from 1 to
16. Clock multiplication and division can be used for time-domain
multiplexing and other functions, which can reduce design LE
requirements.
Table 14
shows the
Clock 2
×1
×2
×4
Altera Corporation

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