IC APEX 20KE FPGA 100K 208-PQFP

 

EP20K100EQC208-3

Manufacturer Part NumberEP20K100EQC208-3
DescriptionIC APEX 20KE FPGA 100K 208-PQFP
ManufacturerAltera
SeriesAPEX-20K®
EP20K100EQC208-3 datasheets

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Specifications of EP20K100EQC208-3

Number Of Logic Elements/cells4160Number Of Labs/clbs416
Total Ram Bits53248Number Of I /o151
Number Of Gates263000Voltage - Supply1.71 V ~ 1.89 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case208-MQFP, 208-PQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-2092  
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Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices (Part 2 of 2)
Symbol
t
Skew delay between related
SKEW
ClockLock/ClockBoost-generated clocks
t
Jitter on ClockLock/ClockBoost-generated clock
JITTER
(5)
t
Input clock stability (measured between adjacent
INCLKSTB
clocks)
Notes to
Table
15:
(1)
The PLL input frequency range for the EP20K100-1X device for 1x multiplication is 25 MHz to 175 MHz.
(2)
All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured first. If the incoming clock is
supplied during configuration, the ClockLock and ClockBoost circuitry locks during configuration, because the lock
time is less than the configuration time.
(4)
The jitter specification is measured under long-term observation.
(5)
If the input clock stability is 100 ps, t
Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade Devices
Symbol
f
Output frequency
OUT
f
Input clock frequency (ClockBoost clock multiplication
CLK1
factor equals 1)
f
Input clock frequency (ClockBoost clock multiplication
CLK2
factor equals 2)
f
Input clock frequency (ClockBoost clock multiplication
CLK4
factor equals 4)
t
Duty cycle for ClockLock/ClockBoost-generated clock
OUTDUTY
f
Input deviation from user specification in the Quartus II
CLKDEV
software (ClockBoost clock multiplication factor equals
one)
(1)
t
Input rise time
R
t
Input fall time
F
t
Time required for ClockLock/ ClockBoost to acquire
LOCK
lock
(3)
t
Skew delay between related ClockLock/ ClockBoost-
SKEW
generated clock
t
Jitter on ClockLock/ ClockBoost-generated clock
JITTER
t
Input clock stability (measured between adjacent
INCLKSTB
clocks)
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Parameter
is 250 ps.
JITTER
Table 16
summarizes the APEX 20K ClockLock and ClockBoost
parameters for -2 speed grade devices.
Parameter
Min
Max
500
200
50
Min
Max
25
170
25
170
16
80
10
34
40
60
25,000
5
5
10
500
500
(4)
200
50
Unit
ps
ps
ps
Unit
MHz
MHz
MHz
MHz
%
(2)
PPM
ns
ns
µs
ps
ps
ps
51

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