EP4CE55F29C9LN | |
|---|---|
| Manufacturer Part Number | EP4CE55F29C9LN |
| Description | IC CYCLONE IV FPGA 55K 780FBGA |
| Manufacturer | Altera |
| Series | CYCLONE® IV E |
| EP4CE55F29C9LN datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
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Specifications of EP4CE55F29C9LN | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 55856 | Number Of Labs/clbs | 3491 |
| Total Ram Bits | 2340000 | Number Of I /o | 374 |
| Voltage - Supply | 0.97 V ~ 1.03 V | Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 85°C | Package / Case | 780-FBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Number Of Gates | - |
EP4CGX15BN11C8N PDF datasheetEP4CGX15BN11C8N PDF datasheet #2EP4CGX15BN11C8N PDF datasheet #3EP4CGX15BN11C8N PDF datasheet #4
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PrevNext
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
The programming hardware or download cable then places the configuration data
one bit at a time on the DATA[0] pin of the device. The configuration data is clocked
into the target device until CONF_DONE goes high. The CONF_DONE pin must have an
external 10-k pull-up resistor for the device to initialize.
When you use a download cable, setting the Auto-restart configuration after error
option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software if an error occurs. Additionally, the Enable
user-supplied start-up clock (CLKUSR) option has no effect on device initialization,
because this option is disabled in the .sof when programming the device with the
Quartus II Programmer and download cable. Therefore, if you turn on the CLKUSR
option, you do not have to provide a clock on CLKUSR when you configure the device
with the Quartus II Programmer and a download cable.
Figure 8–17
shows PS configuration for Cyclone IV devices with a download cable.
Figure 8–17. PS Configuration Using a Download Cable
V
(1)
CCA
10 kΩ
(2)
Notes to
Figure
8–17:
(1) You must connect the pull-up resistor to the same supply voltage as the V
(2) The pull-up resistors on DATA[0] and DCLK are only required if the download cable is the only configuration
scheme used on your board. This is to ensure that DATA[0] and DCLK are not left floating after configuration. For
example, if you also use a configuration device, the pull-up resistors on DATA[0] and DCLK are not required.
(3) Pin 6 of the header is a V
device. For this value, refer to the
ByteBlaster II, ByteBlaster MV, and EthernetBlaster, this pin is a no connect.
(4) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(5) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
refer to
Table 8–3 on page
Connect the MSEL pins directly to V
(6) Power up the V
Third-party programmers must switch to 2.5 V. Pin 4 of the header is a V
The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V from
the USB cable. For this value, refer to the
© December 2010 Altera Corporation
V
(1)
CCA
10 kΩ
(2)
V
(1)
CCA
10 kΩ
Cyclone IV Device
CONF_DONE
nSTATUS
MSEL[ ] (5)
nCE
nCEO
GND
DCLK
DATA[0]
nCONFIG
reference voltage for the MasterBlaster output driver. V
IO
MasterBlaster Serial/USB Communications Cable User
8–8,
Table 8–4 on page
8–8, and
Table 8–5 on page 8–9
or GND.
CCA
of the ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5-V supply from V
CC
MasterBlaster Serial/USB Communications Cable User
8–37
V
(1)
CCA
V
(1)
CCA
10 kΩ
10 kΩ
Download Cable 10-Pin Male
N.C. (4)
Header (Top View)
Pin 1
V
(6)
CCA
GND
V
(3)
IO
Shield
GND
supply.
CCA
must match the V
of the
IO
CCA
Guide. With the USB-Blaster,
for PS configuration schemes.
.
CCA
power supply for the MasterBlaster cable.
CC
Guide.
Cyclone IV Device Handbook, Volume 1
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