EP4CE55F29C9LN | |
|---|---|
| Manufacturer Part Number | EP4CE55F29C9LN |
| Description | IC CYCLONE IV FPGA 55K 780FBGA |
| Manufacturer | Altera |
| Series | CYCLONE® IV E |
| EP4CE55F29C9LN datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
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Specifications of EP4CE55F29C9LN | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 55856 | Number Of Labs/clbs | 3491 |
| Total Ram Bits | 2340000 | Number Of I /o | 374 |
| Voltage - Supply | 0.97 V ~ 1.03 V | Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 85°C | Package / Case | 780-FBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Number Of Gates | - |
EP4CGX15BN11C8N PDF datasheetEP4CGX15BN11C8N PDF datasheet #2EP4CGX15BN11C8N PDF datasheet #3EP4CGX15BN11C8N PDF datasheet #4
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PrevNext
Chapter 11: Power Requirements for Cyclone IV Devices
Hot-socketing Feature Implementation
1
The user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are
always enabled (after POR) before and during configuration. The weak pull up
resistors are not enabled prior to POR.
A possible concern for semiconductor devices in general regarding hot socketing is
the potential for latch up. Latch up can occur when electrical subsystems are hot
socketed into an active system. During hot socketing, the signal pins may be
connected and driven by the active system before the power supply can provide
current to the V
and cause a low-impedance path from V
device extends a large amount of current, possibly causing electrical damage.
The design of the I/O buffers and hot-socketing circuitry ensures that Cyclone IV
devices are immune to latch up during hot-socketing.
f
For more information about the hot-socketing specification, refer to the
Device Datasheet
for Altera Devices
Hot-socketing Feature Implementation
The hot-socketing circuit does not include the CONF_DONE, nCEO, and nSTATUS pins
to ensure that they are able to operate during configuration. The expected behavior
for these pins is to drive out during power-up and power-down sequences.
1
Altera uses GND as reference for hot-socketing operation and I/O buffer designs. To
ensure proper operation, Altera recommends connecting the GND between boards
before connecting the power supplies. This prevents the GND on your board from
being pulled up inadvertently by a path to power through other components on your
board. A pulled up GND can otherwise cause an out-of-specification I/O voltage or
current condition with the Altera device.
Power-On Reset Circuitry
Cyclone IV devices contain POR circuitry to keep the device in a reset state until the
power supply voltage levels have stabilized during power up. During POR, all user
I/O pins are tri-stated until the power supplies reach the recommended operating
levels. In addition, the POR circuitry also ensures the V
contain configuration pins reach an acceptable level before configuration is triggered.
The POR circuit of the Cyclone IV device monitors the V
contain configuration pins during power-on. You can power up or power down the
V
, V
, and V
CCINT
CCA
monotonic rise to their steady state levels. All V
(even when PLLs are not used), and must be powered up and powered down at the
same time.
After the Cyclone IV device enters the user mode, the POR circuit continues to
monitor the V
detected. If the V
mode, the POR circuit resets the device. If the V
the POR circuit does not reset the device.
© July 2010 Altera Corporation
of the device and ground planes. This condition can lead to latch up
CC
to GND in the device. As a result, the
CC
chapter and the
Hot-Socketing and Power-Sequencing Feature and Testing
white paper.
pins in any sequence. The V
CCIO
and V
pins so that a brown-out condition during user mode is
CCINT
CCA
or V
voltage sags below the POR trip point during user
CCINT
CCA
Cyclone IV
level of I/O banks that
CCIO
, V
, and V
that
CCINT
CCA
CCIO
, V
, and V
must have a
CCINT
CCA
CCIO
pins must be powered to 2.5V
CCA
voltage sags during user mode,
CCIO
Cyclone IV Device Handbook, Volume 1
11–3
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