EP4CE55F29C9LN

Manufacturer Part NumberEP4CE55F29C9LN
DescriptionIC CYCLONE IV FPGA 55K 780FBGA
ManufacturerAltera
SeriesCYCLONE® IV E
EP4CE55F29C9LN datasheets

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Specifications of EP4CE55F29C9LN

Number Of Logic Elements/cells55856Number Of Labs/clbs3491
Total Ram Bits2340000Number Of I /o374
Voltage - Supply0.97 V ~ 1.03 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case780-FBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
EP4CGX15BN11C8N PDF datasheetEP4CGX15BN11C8N PDF datasheet #2EP4CGX15BN11C8N PDF datasheet #3EP4CGX15BN11C8N PDF datasheet #4
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Download datasheet (13Mb)Embed
PrevNext
2–2
Figure 2–1
shows the LEs for Cyclone IV devices.
Figure 2–1. Cyclone IV Device LEs
LE Carry-In
data 1
data 2
Look-Up Table
data 3
(LUT)
data 4
Register Feedback
LE Features
You can configure the programmable register of each LE for D, T, JK, or SR flipflop
operation. Each register has data, clock, clock enable, and clear inputs. Signals that
use the global clock network, general-purpose I/O pins, or any internal logic can
drive the clock and clear control signals of the register. Either general-purpose I/O
pins or the internal logic can drive the clock enable. For combinational functions, the
LUT output bypasses the register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing resources.
The LUT or register output independently drives these three outputs. Two LE outputs
drive the column or row and direct link routing connections, while one LE drives the
local interconnect resources. This allows the LUT to drive one output while the
register drives another output. This feature, called register packing, improves device
utilization because the device can use the register and the LUT for unrelated
functions. The LAB-wide synchronous load control signal is not available when using
register packing. For more information about the synchronous load control signal,
refer to
“LAB Control Signals” on page
The register feedback mode allows the register output to feed back into the LUT of the
same LE to ensure that the register is packed with its own fan-out LUT, providing
another mechanism for improved fitting. The LE can also drive out registered and
unregistered versions of the LUT output.
Cyclone IV Device Handbook, Volume 1
Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices
Register Chain
Register Bypass
LAB-Wide
Routing from
Synchronous
LAB-Wide
previous LE
Load
Synchronous
Clear
Synchronous
Carry
Load and
Chain
Clear Logic
labclr1
labclr2
Asynchronous
Chip-Wide
Clear Logic
Reset
(DEV_CLRn)
Clock &
Clock Enable
Select
labclk1
LE Carry-Out
labclk2
labclkena1
labclkena2
2–6.
Logic Elements
Row, Column,
And Direct Link
D
Q
Routing
ENA
CLRN
Row, Column,
And Direct Link
Routing
Local
Routing
Register Chain
Output
© November 2009 Altera Corporation

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