EP4CE55F29C9LN | |
|---|---|
| Manufacturer Part Number | EP4CE55F29C9LN |
| Description | IC CYCLONE IV FPGA 55K 780FBGA |
| Manufacturer | Altera |
| Series | CYCLONE® IV E |
| EP4CE55F29C9LN datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
- We ship worldwide using main international couriers like FedEx, DHL, UPS, TNT, EMS. We can also use client's freight account. Other shipping methods can be discussed. We do best to meet your needs!
Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of EP4CE55F29C9LN | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 55856 | Number Of Labs/clbs | 3491 |
| Total Ram Bits | 2340000 | Number Of I /o | 374 |
| Voltage - Supply | 0.97 V ~ 1.03 V | Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 85°C | Package / Case | 780-FBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Number Of Gates | - |
EP4CGX15BN11C8N PDF datasheetEP4CGX15BN11C8N PDF datasheet #2EP4CGX15BN11C8N PDF datasheet #3EP4CGX15BN11C8N PDF datasheet #4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
PrevNext
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
FPGA Fabric-Transceiver Interface Clocking
The FPGA fabric-transceiver interface clocks consists of clock signals from the FPGA
fabric to the transceiver blocks, and from the transceiver blocks to the FPGA fabric.
These clock resources use the global clock networks (GCLK) in the FPGA core.
f
For information about the GCLK resources in the Cyclone IV GX devices, refer to
Clock Networks and PLLs in Cyclone IV Devices
Table 1–11
lists the FPGA fabric-transceiver interface clocks.
Table 1–11. FPGA Fabric-Transceiver Interface Clocks
Clock Name
Phase compensation FIFO clock
tx_clkout
Phase compensation FIFO clock
rx_clkout
Phase compensation FIFO clock
coreclkout
125MHz receiver detect clock in PIPE
fixed_clk
reconfig_clk (1),
Transceiver dynamic reconfiguration and
(2)
offset cancellation clock
(2)
Transceiver calibration block clock
cal_blk_clk
:
Notes to
Table 1–11
(1) Offset cancellation process that is executed after power cycle requires reconfig_clk clock. The reconfig_clk must be driven with a
free-running clock and not derived from the transceiver blocks.
(2) For the supported clock frequency range, refer to the
In the transmitter datapath, TX phase compensation FIFO forms the FPGA
fabric-transmitter interface. Data and control signals for the transmitter are clocked
with the FIFO write clock. The FIFO write clock supports automatic clock selection by
the Quartus II software (depending on channel configuration), or user-specified clock
from tx_coreclk port.
FIFO write clock selection by the Quartus II software.
1
The Quartus II software assumes automatic clock selection for TX phase
compensation FIFO write clock if you do not enable the tx_coreclk port.
Table 1–12. Automatic TX Phase Compensation FIFO Write Clock Selection
Channel Configuration
tx_clkout clock feeds the FIFO write clock. tx_clkout is forwarded through the transmitter
Non-bonded
channel from low-speed clock, which also feeds the FIFO read clock.
coreclkout clock feeds the FIFO write clock for the bonded channels. coreclkout clock is
Bonded
the common bonded low-speed clock, which also feeds the FIFO read clock in the bonded channels.
When using user-specified clock option, ensure that the clock feeding tx_coreclk
port has 0 PPM difference with the TX phase compensation FIFO read clock.
© December 2010 Altera Corporation
chapter.
Clock Description
mode
Cyclone IV Device Data
Sheet.
Table 1–12
details the automatic TX phase compensation
Quartus II Selection
1–39
Interface Direction
Transceiver to FPGA fabric
Transceiver to FPGA fabric
Transceiver to FPGA fabric
FPGA fabric to transceiver
FPGA fabric to transceiver
FPGA fabric to transceiver
Cyclone IV Device Handbook, Volume 2
Related parts for EP4CE55F29C9LN | |||
|---|---|---|---|
| Part Number | Description | Manufacturer | Datasheet |
 EP4CE55F23C8N |
IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
|
|
EP4CE55F23C9LN |
IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
|
|
EP4CE55F29C8N |
IC CYCLONE IV FPGA 55K 780FBGA | Altera Corporation |
|
|
EP4CE55F23C8 |
IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
|
|
EP4CE55F23C9L |
IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
|
|
EP4CE55F29C8 |
IC CYCLONE IV FPGA 55K 780FBGA | Altera Corporation |
|
|
EP4CE55F29C9L |
IC CYCLONE IV FPGA 55K 780FBGA | Altera Corporation |
|
|
EP4CE55F23C8LN |
IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
|
|
EP4CE55F29C8LN |
IC CYCLONE IV FPGA 55K 780FBGA | Altera Corporation |
|
|
EP4CE55F23C7 |
IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
|
|
EP4CE55F23C8L |
IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
|
|
EP4CE55F29C7 |
IC CYCLONE IV FPGA 55K 780FBGA | Altera Corporation |
|
|
EP4CE55F29C8L |
IC CYCLONE IV FPGA 55K 780FBGA | Altera Corporation |
|
|
EP4CE55F23C6N |
IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
|
|
EP4CE55F23I7N |
IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
|
