EP4CE55F29C9LN | |
|---|---|
| Manufacturer Part Number | EP4CE55F29C9LN |
| Description | IC CYCLONE IV FPGA 55K 780FBGA |
| Manufacturer | Altera |
| Series | CYCLONE® IV E |
| EP4CE55F29C9LN datasheets |
|
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Specifications of EP4CE55F29C9LN | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 55856 | Number Of Labs/clbs | 3491 |
| Total Ram Bits | 2340000 | Number Of I /o | 374 |
| Voltage - Supply | 0.97 V ~ 1.03 V | Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 85°C | Package / Case | 780-FBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Number Of Gates | - |
EP4CGX15BN11C8N PDF datasheetEP4CGX15BN11C8N PDF datasheet #2EP4CGX15BN11C8N PDF datasheet #3EP4CGX15BN11C8N PDF datasheet #4
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Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Figure 2–2
shows the transceiver reset sequences for Cyclone IV GX devices.
Figure 2–2. Transceiver Reset Sequences Chart
Dynamic Reconfiguration
Reset Sequence
Reset Sequence
for PLL
for channel
reconfiguration mode
reconfiguration mode
‘Transmitter Only’
channel (2)
Notes to
Figure
2–2:
(1) Refer to the Timing Diagram in
Figure
2–10.
(2) Refer to the Timing Diagram in
Figure
2–3.
(3) Refer to the Timing Diagram in
Figure
2–4.
(4) Refer to the Timing Diagram in
Figure
2–5.
(5) Refer to the Timing Diagram in
Figure
2–6.
(6) Refer to the Timing Diagram in
Figure
2–7.
(7) Refer to the Timing Diagram in
Figure
2–8.
(8) Refer to the Timing Diagram in
Figure
2–9.
All Supported Functional Modes Except the PCIe Functional Mode
This section describes reset sequences for transceiver channels in bonded and
non-bonded configurations. Timing diagrams of some typical configurations are
shown to facilitate proper reset sequence implementation. In these functional modes,
you can set the receiver CDR either in automatic lock or manual lock mode.
1
In manual lock mode, the receiver CDR locks to the reference clock (lock-to-reference)
or the incoming serial data (lock-to-data), depending on the logic levels on the
rx_locktorefclk and rx_locktodata signals. With the receiver CDR in manual
lock mode, you can either configure the transceiver channels in the Cyclone IV GX
device in a non-bonded configuration or a bonded configuration. In a bonded
configuration, for example in XAUI mode, four channels are bonded together.
© December 2010 Altera Corporation
Transceiver
initialization reset
sequences
All supported
functional modes
except PCI Express (PCIe)
Bonded
Non-Bonded
‘Receiver and
‘Transmitter Only’
Transmitter’
channel (2)
channel
Receiver CDR
Receiver CDR
Receiver CDR
in automatic
in manual
in automatic
lock mode
lock mode
lock mode
(3)
(4)
(5)
2–5
PCI Express
(PIPE)
Initialization/
Compliance and
Normal Operation
Phases (1)
‘Receiver and
‘Receiver Only’
Transmitter’
channel
channel
Receiver CDR
Receiver CDR
Receiver CDR
in manual
in automatic
in manual
lock mode
lock mode
lock mode
(6)
(7)
(8)
Cyclone IV Device Handbook, Volume 2
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IC CYCLONE IV FPGA 55K 780FBGA | Altera Corporation |
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IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
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IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
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IC CYCLONE IV FPGA 55K 780FBGA | Altera Corporation |
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IC CYCLONE IV FPGA 55K 780FBGA | Altera Corporation |
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IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
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IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
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