EP4CE55F29C9LN

Manufacturer Part NumberEP4CE55F29C9LN
DescriptionIC CYCLONE IV FPGA 55K 780FBGA
ManufacturerAltera
SeriesCYCLONE® IV E
EP4CE55F29C9LN datasheets

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Specifications of EP4CE55F29C9LN

Number Of Logic Elements/cells55856Number Of Labs/clbs3491
Total Ram Bits2340000Number Of I /o374
Voltage - Supply0.97 V ~ 1.03 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case780-FBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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PrevNext
Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. When the
receiver CDR is in manual lock mode, use the reset sequence shown in
Figure 2–5. Sample Reset Sequence for Bonded Configuration Receiver and Transmitter Channels—Receiver CDR in Manual
Lock Mode
Reset Signals
1 µs
1
2
pll_areset
(txurstpcs) tx_digitalreset
(rxurstpma) rx_analogreset
(rxurstpcs) rx_digitalreset
CDR Control Signals
rx_locktorefclk[0]
rx_locktorefclk[n] (2)
rx_locktodata[0]
rx_locktodata[n] (2)
Output Status Signals
pll_locked
busy (4)
Notes to
Figure
2–5:
(1) For t
duration, refer to the
Cyclone IV Device Datasheet
LTD_Manual
(2) The number of rx_locktorefclk[n] and rx_locktodata[n] signals depend on the number of channels configured. n=number of
channels.
(3) For t
duration, refer to the
Cyclone IV Device Datasheet
LTR_LTD_Manual
(4) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the
busy signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
As shown in
in manual lock mode configuration:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
between markers 1 and 2).
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
rx_locktorefclk signals asserted and the rx_locktodata signal deasserted
during this time period. After you deassert the pll_areset signal, the
multipurpose PLL starts locking to the input reference clock.
© December 2010 Altera Corporation
4
6
t
7
7
t
(3)
LTR_LTD_Manual
7
7
3
Two parallel clock cycles
5
chapter.
chapter.
Figure
2–5, perform the following reset procedure for the receiver CDR
Figure
2–5.
8
(1)
LTD_Manual
Cyclone IV Device Handbook, Volume 2
2–9

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