EP4CE55F29C9LN | |
|---|---|
| Manufacturer Part Number | EP4CE55F29C9LN |
| Description | IC CYCLONE IV FPGA 55K 780FBGA |
| Manufacturer | Altera |
| Series | CYCLONE® IV E |
| EP4CE55F29C9LN datasheets |
|
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Warranty: 60 days
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Specifications of EP4CE55F29C9LN | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 55856 | Number Of Labs/clbs | 3491 |
| Total Ram Bits | 2340000 | Number Of I /o | 374 |
| Voltage - Supply | 0.97 V ~ 1.03 V | Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 85°C | Package / Case | 780-FBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Number Of Gates | - |
EP4CGX15BN11C8N PDF datasheetEP4CGX15BN11C8N PDF datasheet #2EP4CGX15BN11C8N PDF datasheet #3EP4CGX15BN11C8N PDF datasheet #4
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PrevNext
2–18
Dynamic Reconfiguration Reset Sequences
When using dynamic reconfiguration in data rate divisions in PLL reconfiguration or
channel reconfiguration mode, use the following reset sequences.
Reset Sequence in PLL Reconfiguration Mode
Use the example reset sequence shown in
reconfiguration controller to change the data rate of the transceiver channel. In this
example, PLL dynamic reconfiguration is used to dynamically reconfigure the data
rate of the transceiver channel configured in Basic ×1 mode with the receiver CDR in
automatic lock mode.
Figure 2–11. Reset Sequence When Using the PLL Dynamic Reconfiguration Controller to Change
the Data Rate of the Transceiver Channel
Reset and Control Signals
tx_digitalreset
rx_analogreset
rx_digitalreset
pll_configupdate (1)
pll_areset (1)
Output Status Signals
pll_reconfig_done
pll_locked
rx_freqlocked
Notes to
Figure
2–11:
(1) The pll_configupdate and pll_areset signals are driven by the ALTPLL_RECONFIG megafunction. For
more information, refer to
Cyclone IV Dynamic Reconfiguration
(2) For t
duration, refer to the
LTD_Auto
As shown in
dynamic reconfiguration controller to change the configuration of the PLLs in the
transmitter channel:
1. Assert the tx_digitalreset, rx_analogreset, and rx_digitalreset
signals. The pll_configupdate signal is asserted (marker 1) by the
ALTPLL_RECONFIG megafunction after the final data bit is sent out. The
pll_reconfig_done signal is asserted (marker 2) to inform the
ALTPLL_RECONFIG megafunction that the scan chain process is completed. The
ALTPLL_RECONFIG megafunction then asserts the pll_areset signal (marker
3) to reset the transceiver PLL.
Cyclone IV Device Handbook, Volume 2
Chapter 2: Cyclone IV Reset Control and Power Down
Figure 2–11
1
3
2
AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX Devices
chapter.
Cyclone IV Device Datasheet
Figure
2–11, perform the following reset procedure when using the PLL
Dynamic Reconfiguration Reset Sequences
when you use the PLL dynamic
5
6
8
Five parallel clock cycles
4
7
t
(2)
LTD_Auto
and the
chapter.
© December 2010 Altera Corporation
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