EP4CE55F29C9LN | |
|---|---|
| Manufacturer Part Number | EP4CE55F29C9LN |
| Description | IC CYCLONE IV FPGA 55K 780FBGA |
| Manufacturer | Altera |
| Series | CYCLONE® IV E |
| EP4CE55F29C9LN datasheets |
|
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Specifications of EP4CE55F29C9LN | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 55856 | Number Of Labs/clbs | 3491 |
| Total Ram Bits | 2340000 | Number Of I /o | 374 |
| Voltage - Supply | 0.97 V ~ 1.03 V | Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 85°C | Package / Case | 780-FBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Number Of Gates | - |
EP4CGX15BN11C8N PDF datasheetEP4CGX15BN11C8N PDF datasheet #2EP4CGX15BN11C8N PDF datasheet #3EP4CGX15BN11C8N PDF datasheet #4
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Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Method 3: Writing Different Control Signals for all the Transceiver Channels at the
Same Time
If you disable the Use the same control signal for all the channels option, the PMA
control ports for a write transaction are separate for each channel. If you disable this
option, the width of the PMA control ports are fixed as follows:
PMA Control Ports Used in a Write Transaction
tx_vodctrl is 3 bits per channel
■
■
tx_preemp are 5 bits per channel
■
rx_eqdcgain is 2 bits per channel
■
rx_eqctrl is 4 bits per channel
For example, if you have two channels, the tx_vodctrl is 6 bits wide
(tx_vodctrl [2:0] corresponds to channel 1 and tx_vodctrl [5:3] corresponds to
channel 2).
PMA Control Ports Used in a Read Transaction
The width of the PMA control ports for a read transaction are always separate for each
channel as explained in
the Transceiver Channels” on page
Write Transaction
Because the PMA controls of all the channels are written, if you want to reconfigure a
specific channel connected to the ALTGX_RECONFIG instance, set the new value at
the corresponding PMA control port of the channel under consideration and retain
the previously stored values in the other active channels with a read transaction prior
to this write transaction.
For example, if the number of channels controlled by the ALTGX_RECONFIG
instance is two, the tx_vodctrl signal in this case would be 6 bits wide. The
tx_vodctrl[2:0] signal corresponds to channel 1 and the tx_vodctrl[5:3] signal
corresponds to channel 2.
■
To dynamically reconfigure the PMA controls of only channel 2 with a new value,
first perform a read transaction to retrieve the existing PMA control values from
tx_vodctrl_out[5:0]. Use the tx_vodctrl_out[2:0] value for tx_vodctrl[2:0]
to write in channel 1. By doing so, channel 1 is overwritten with the same value.
Perform a write transaction. This ensures that the new values are written only to
■
channel 2 while channel 1 remains unchanged.
© December 2010 Altera Corporation
“Method 2: Writing the Same Control Signals to Control All
3–14.
Cyclone IV Device Handbook, Volume 2
3–17
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IC CYCLONE IV FPGA 55K 484FBGA | Altera Corporation |
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