EP4CE55F29C9LN | |
|---|---|
| Manufacturer Part Number | EP4CE55F29C9LN |
| Description | IC CYCLONE IV FPGA 55K 780FBGA |
| Manufacturer | Altera |
| Series | CYCLONE® IV E |
| EP4CE55F29C9LN datasheets |
|
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Specifications of EP4CE55F29C9LN | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 55856 | Number Of Labs/clbs | 3491 |
| Total Ram Bits | 2340000 | Number Of I /o | 374 |
| Voltage - Supply | 0.97 V ~ 1.03 V | Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 85°C | Package / Case | 780-FBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Number Of Gates | - |
EP4CGX15BN11C8N PDF datasheetEP4CGX15BN11C8N PDF datasheet #2EP4CGX15BN11C8N PDF datasheet #3EP4CGX15BN11C8N PDF datasheet #4
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Chapter 4: Embedded Multipliers in Cyclone IV Devices
Architecture
Architecture
Each embedded multiplier consists of the following elements:
■
Multiplier stage
Input and output registers
■
■
Input and output interfaces
Figure 4–2
shows the multiplier block architecture.
Figure 4–2. Multiplier Block Architecture
Data A
Data B
Input Registers
You can send each multiplier input signal into an input register or directly into the
multiplier in 9- or 18-bit sections, depending on the operational mode of the
multiplier. You can send each multiplier input signal through a register independently
of other input signals. For example, you can send the multiplier Data A signal
through a register and send the Data B signal directly to the multiplier.
The following control signals are available for each input register in the embedded
multiplier:
clock
■
■
clock enable
■
asynchronous clear
All input and output registers in a single embedded multiplier are fed by the same
clock, clock enable, and asynchronous clear signals.
Multiplier Stage
The multiplier stage of an embedded multiplier block supports 9 × 9 or 18 × 18
multipliers, as well as other multipliers between these configurations. Depending on
the data width or operational mode of the multiplier, a single embedded multiplier
can perform one or two multiplications in parallel. For multiplier information, refer to
“Operational Modes” on page
© February 2010 Altera Corporation
signa
signb
aclr
clock
ena
D
Q
ENA
D
Q
CLRN
ENA
CLRN
D
Q
ENA
Output
Register
Input
Register
CLRN
Embedded Multiplier Block
4–4.
Cyclone IV Device Handbook, Volume 1
4–3
Data Out
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