EP4CE55F29C9LN

Manufacturer Part NumberEP4CE55F29C9LN
DescriptionIC CYCLONE IV FPGA 55K 780FBGA
ManufacturerAltera
SeriesCYCLONE® IV E
EP4CE55F29C9LN datasheets

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Specifications of EP4CE55F29C9LN

Number Of Logic Elements/cells55856Number Of Labs/clbs3491
Total Ram Bits2340000Number Of I /o374
Voltage - Supply0.97 V ~ 1.03 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case780-FBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
EP4CGX15BN11C8N PDF datasheetEP4CGX15BN11C8N PDF datasheet #2EP4CGX15BN11C8N PDF datasheet #3EP4CGX15BN11C8N PDF datasheet #4
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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
Figure 5–23
shows a functional simulation of the PLL reconfiguration feature.
Figure 5–23. PLL Reconfiguration Scan Chain
scandata
D0 (LSB)
scanclk
scanclkena
scandataout
D0_old
configupdate
scandone
areset
1
When reconfiguring the counter clock frequency, the corresponding counter phase
shift settings cannot be reconfigured using the same interface. You can reconfigure
phase shifts in real time using the dynamic phase shift reconfiguration interface. If
you reconfigure the counter frequency, but wish to keep the same non-zero phase shift
setting (for example, 90°) on the clock output, you must reconfigure the phase shift
after reconfiguring the counter clock frequency.
Post-Scale Counters (C0 to C4)
You can configure multiply or divide values and duty cycle of post-scale counters in
real time. Each counter has an 8-bit high time setting and an 8-bit low time setting.
The duty cycle is the ratio of output high or low time to the total cycle time, that is the
sum of the two. Additionally, these counters have two control bits, rbypass, for
bypassing the counter, and rselodd, to select the output clock duty cycle.
When the rbypass bit is set to 1, it bypasses the counter, resulting in a divide by one.
When this bit is set to 0, the PLL computes the effective division of the VCO output
frequency based on the high and low time counters. For example, if the post-scale
divide factor is 10, the high and low count values are set to 5 and 5, to achieve a
50–50% duty cycle. The PLL implements this duty cycle by transitioning the output
clock from high-to-low on the rising edge of the VCO output clock. However, a 4 and
6 setting for the high and low count values, respectively, would produce an output
clock with a 40–60% duty cycle.
© December 2010 Altera Corporation
5–37
Dn (MSB)
Dn_old
Dn
Cyclone IV Device Handbook, Volume 1

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