EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet

IC STRATIX GX FPGA 10KLE 672FBGA

EP1SGX10DF672C5N

Manufacturer Part Number
EP1SGX10DF672C5N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet

Specifications of EP1SGX10DF672C5N

Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Altera Corporation
This section provides the data sheet specifications for Stratix
devices. It contains feature definitions of the internal architecture,
configuration information, testing information, DC operating conditions,
and AC timing parameters.
This section includes the following chapters:
Chapter 1, Introduction to the Stratix GX Device Data Sheet
Chapter 2, Stratix GX Transceivers
Chapter 3, Source-Synchronous Signaling With DPA
Chapter 4, Stratix GX Architecture
Chapter 5, Configuration & Testing
Chapter 6, DC & Switching Characteristics
Chapter 7, Reference & Ordering Information
Device Family Data Sheet
Section I. Stratix GX
®
Preliminary
Section I–1
GX

Related parts for EP1SGX10DF672C5N

EP1SGX10DF672C5N Summary of contents

Page 1

... This section includes the following chapters: ■ ■ ■ ■ ■ ■ ■ Altera Corporation Section I. Stratix GX Device Family Data Sheet Chapter 1, Introduction to the Stratix GX Device Data Sheet Chapter 2, Stratix GX Transceivers Chapter 3, Source-Synchronous Signaling With DPA Chapter 4, Stratix GX Architecture Chapter 5, Configuration & Testing Chapter 6, DC & ...

Page 2

... Comments section. Changed ● receiver input voltage and refclkb input voltage in Table 6–4. ● Changed value for undershoot during transition from -0 -2 note 3 of Table 6–6. ● Changed value Table 6–15. ● Changed unit value Ω .. Altera Corporation for from ...

Page 3

... Features Altera Corporation February 2005 1. Introduction to the Stratix GX Device Data Sheet ® GX family of devices is Altera’s second FPGA family to Transceiver block features are as follows: High-speed serial transceiver channels with CDR provides ● 500-megabits per second (Mbps) to 3.1875-Gbps full-duplex operation Devices are available with high-speed serial ● ...

Page 4

... SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM Support for multiple intellectual property megafunctions from ● ® ® Altera MegaCore functions and Altera Megafunction Partners Program (AMPP ) megafunctions SM Support for remote configuration updates ● Dynamic phase alignment on LVDS receiver channels ● ...

Page 5

... The Quartus II software can automatically cross reference and place all pins for migration when given a device migration list. Table 1–2. Stratix GX Package Options & I/O Pin Counts (Part EP1SGX10C EP1SGX10D EP1SGX25C Altera Corporation February 2005 Introduction to the Stratix GX Device Data Sheet EP1SGX10C EP1SGX10D 10,570 ...

Page 6

... Device 672-Pin FineLine BGA -5, -6, -7 -5, -6, -7 Figure 1–1 1,020-Pin FineLine BGA 607 607 624 624 672 Pin 1,020 Pin 1.00 1.00 729 1,089 27 × × 33 1,020-pin FineLine BGA -5, -6, -7 -5, -6, -7 shows the Stratix GX I/O blocks. Altera Corporation February 2005 ...

Page 7

... A series of column and row Description interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks. Altera Corporation February 2005 Introduction to the Stratix GX Device Data Sheet Note (1) DQST4 DQST3 ...

Page 8

... DDR SDRAM, FCRAM, ZBT, and QDR SRAM devices. High-speed serial interface channels support transfers 840 Mbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure 1–2 1–6 Stratix GX Device Handbook, Volume 1 shows an overview of the Stratix GX device. Altera Corporation February 2005 ...

Page 9

... Device Columns/Blocks Columns/Blocks EP1SGX10 EP1SGX25 6 / 224 EP1SGX40 8 / 384 Altera Corporation February 2005 Introduction to the Stratix GX Device Data Sheet M4K RAM Blocks DSP Blocks for for True Dual-Port IOEs Support DDR, PCI, GTL+, SSTL-3, Multiplication and Full Memory & Other Embedded SSTL-2, HSTL, LVDS, LVPECL, PCML, ...

Page 10

... FPGA Functional Description 1–8 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 ...

Page 11

... The receiver PLL within each transceiver channel generates the receiver reference clocks. The supporting logic also contains state machines to manage rate matching for XAUI and GIGE applications, in addition to channel bonding for XAUI applications. Altera Corporation June 2006 2. Stratix GX Transceivers ® ...

Page 12

... Receiver Channel 2 Channel 2 Transmitter Channel 2 Receiver Channel 3 Channel 3 Transmitter Channel 3 2–13. “Transmitter Path” on page Receiver Pins Transmitter Pins Receiver Pins Transmitter Pins PLD Logic Array PLL (2) Receiver Pins Transmitter Pins Receiver Pins Transmitter Pins 2–5. Altera Corporation June 2006 ...

Page 13

... BIST and pseudo-random binary sequence pattern generator/verifier. The PMA portion of the transceiver consists of the serializer/deserializer, the CRU, and the I/O buffers. Altera Corporation June 2006 Transmitter PLL Transmitter phase compensation FIFO buffer Byte serializer ...

Page 14

... Figure 2–2. Stratix GX Transceiver ChanneL Note to Figure 2–2: (1) There are four transceiver channels in a transceiver block. 2–4 Stratix GX Device Handbook, Volume 1 Note (1) Altera Corporation June 2006 ...

Page 15

... The transmitter PLL is also used to train the receiver PLL transmit channels are used in the transceiver block, the transmitter PLL can be turned off. PLL. Altera Corporation June 2006 Figure 2–2). Data travels through the Stratix GX transmitter via the Transmitter PLL ...

Page 16

... Figure 2–3. Transmitter PLL Block Diagram Note to (1) 2–6 Stratix GX Device Handbook, Volume 1 Figure 2–3: The divider in the PLL divides 10, 16, or 20. Note (1) Altera Corporation June 2006 ...

Page 17

... The transmit data path after the byte serializer is single width ( bits). The byte serializer is bypassed when single width mode ( bits) is used at the PLD interface. Altera Corporation June 2006 lists the adjustable parameters in the transmitter PLL. Parameter Table 2– ...

Page 18

... The GIGE transmit state machine can be statically disabled in the Quartus II software, even if using the GIGE protocol mode. 2–8 Stratix GX Device Handbook, Volume 1 Figure 2– 8b-10b conversion MSB sent last diagrams the encoding + ctrl LSB sent first Altera Corporation June 2006 ...

Page 19

... Serializer (Parallel-to-Serial Converter) The serializer converts the parallel 8-bit or 10-bit data into a serial stream, transmitting the LSB first. The serialized stream is then fed to the transmit buffer. Altera Corporation June 2006 Table 2–3 shows the code conversion. XGMII TXD PCS Code-Group ...

Page 20

... The output buffer, as shown in output driver and a programmable pre-emphasis circuit. 2–10 Stratix GX Device Handbook, Volume 1 10 Low-speed High-speed serial clock Figure Serial data D0 D0 out (to output buffer) 2–6, consists of a programmable Altera Corporation June 2006 ...

Page 21

... V OD internal or external termination at the source. Table 2–4. Programmable V 100 120 150 Note to (1) Altera Corporation June 2006 Output Buffer Programmable Pre-Emphasis Programmable Output Driver shows the available settings for each termination value. The can be dynamically or statically set. The output driver requires either ...

Page 22

... Figure 2–8. Programmable Pre-Emphasis Model 2–12 Stratix GX Device Handbook, Volume (Differential (single-ended Bit Bit Time Time Positive Channel ( Negative Channel ( Ground p − Figure 2–8. The pre-emphasis can be V (p-p) V (p- Altera Corporation June 2006 ...

Page 23

... The Stratix GX receiver input buffer supports the 1.5-V PCML I/O standard at a rate up to 3.1875 Gbps. Additional I/O standards, LVDS, 3.3-V PCML, and LVPECL can be supported when AC coupled. The common mode of the input buffer is 1.1 V. The receiver can support Stratix GX-to-Stratix GX DC coupling. Altera Corporation June 2006 V CM Programmable ...

Page 24

... Programmable termination Programmable equalizer Programmable Termination Programmable Equalizer Figure 2–11 shows the setup for programmable receiver 50, 60 Ω 50, 60 Ω Figure 2–12 Differential Input Buffer Differential Input Buffer shows an example of an Altera Corporation June 2006 ...

Page 25

... Each transceiver block has four receiver PLLs and CRUs, each of which is dedicated to a receive channel. If the receive channel associated with a particular receiver PLL or CRU is not used, then the receiver PLL or CRU is powered down for the channel. PLL and CRU circuits. Altera Corporation June 2006 Receiver External Termination and Biasing V DD 50/60/75- Ω ...

Page 26

... PFD up down Charge Pump up RX CRUCLK and Loop Filter down CRU lists the adjustable parameters of the receiver PLL and CRU. All Parameter VCO rx_freqlocked[] rx_riv[ ] High-speed RCVD_CLK Low-speed RCVD_CLK Specifications 25 MHz to 650 MHz 500 Mbps to 3.1875 Gbps Altera Corporation June 2006 ...

Page 27

... Table 2–6. Possible Combinations of rx_lockedtorefclk & rx_locktodata If the rx_lockedtorefclk and rx_locktodata ports are not used, the default is auto mode. Altera Corporation June 2006 10-bit or 20-bit mode 160 in steps of 8-bit or 16-bit mode 128 in steps of 4 Table 2– ...

Page 28

... SONET modes. The word aligner also has two non-customizable modes of operation, which are the XAUI and GIGE modes. Figure 2–15 2–18 Stratix GX Device Handbook, Volume High-speed serial clock Low-speed parallel clock shows the word aligner in bit-slip mode. Figure 2– Altera Corporation June 2006 ...

Page 29

... The pattern detector is active in the bit-slip mode, and it detects the user-defined pattern that is specified in the MegaWizard Manager. The bit-slip mode is available only in Custom mode and SONET mode. Figure 2–16 Altera Corporation June 2006 Patterm Detector 10-Bit 16-Bit 7-Bit ...

Page 30

... SONET mode and cannot be used in the Custom mode. Figure 2–17 2–20 Stratix GX Device Handbook, Volume 1 Pattern Detector 16-Bit Mode A1A2 A1A1A2A2 Mode Mode A1A2 Mode shows the word aligner in 10-bit mode. Word Aligner Manual Alignment Mode 16-Bit Mode A1A1A2A2 Mode Altera Corporation June 2006 ...

Page 31

... A user-controlled enable port is available for the word aligner. The 10-bit mode is available only for the Custom mode. Figure 2–18 Altera Corporation June 2006 Pattern Detector 10-Bit 7-Bit ...

Page 32

... Figure 2–19 the channel alignment after the channel aligner. 2–22 Stratix GX Device Handbook, Volume 1 Word Aligner GigE Mode shows misaligned channels before the channel aligner and Synchronization State Machines XAUI Mode Altera Corporation June 2006 ...

Page 33

... The rate matcher does not perform a clock compensation on any other ordered set combinations. An /I2/ is added or deleted automatically based on the number of words in the FIFO buffer. A 9’h19C is given at the control and data ports when the FIFO overflow or underflow condition. Altera Corporation June 2006 ...

Page 34

... Invalid code groups Disparity errors 2–24 Stratix GX Device Handbook, Volume MSB received last 8b-10b conversion Parallel data Types of Errors rx_errdetect 1’b0 1’b1 1’ LSB received first + ctrl Table 2–7 shows the values of the rx_disperr 1’b0 1’b0 1’b1 Altera Corporation June 2006 ...

Page 35

... PLD core. The phase compensation FIFO buffer is four words deep and cannot be bypassed. Altera Corporation June 2006 PCS code-group Dxx.y Normal Data K28 ...

Page 36

... Serial loopback Parallel loopback Reverse serial loopback Figure 2–21 Rate Matcher 8B/10B Decoder Byte 8B/10B Serializer Encoder BIST PRBS Generator of the OD shows the data path in BIST Incremental Verifier Phase Compensation Byte FIFO Deserializer Phase Compensation BIST FIFO Generator Altera Corporation June 2006 ...

Page 37

... This loopback mode is dynamically switchable through the tx_srlpbk port on a channel by channel basis. Asserting rxanalogreset in reverse serial loopback mode powers down the receiver buffer and CRU, preventing data loopback. the data path in reverse serial loopback mode. Altera Corporation June 2006 Rate Matcher 8B/10B ...

Page 38

... PRBS generator and verifier Incremental mode generator and verifier High-frequency generator Low-frequency generator Mixed-frequency generator and 2–25 are diagrams of the BIST PRBS data path and the BIST Incremental Verifier Phase Compensation Byte FIFO Deserializer Phase Compensation FIFO BIST Generator Altera Corporation June 2006 ...

Page 39

... Non-active Path Table 2–9 Table 2–9. BIST Data Output & Verifier Alignment Pattern (Part BIST Mode Output PRBS 8-bit 8 2 – 1 PRBS 10-bit 10 2 – 1 Altera Corporation June 2006 Verifier Rate Matcher 8B/10B Decoder Byte 8B/10B Serializer Encoder BIST PRBS Generator ...

Page 40

... EP1SGX40G devices. For devices with fewer transceivers, ignore the information about the unavailable transceiver blocks. 2–30 Stratix GX Device Handbook, Volume 1 Polynomials Verifier Word Alignment Pattern 1000000011111111 1111111111 0101111100 (K28.5) (1) 0101111100 (K28.5) (1) and 2–27 are diagrams of the Inter-Transceiver line Altera Corporation June 2006 ...

Page 41

... Figure 2–26: (1) IQ lines are inter-transceiver block lines. (2) If the /2 pre-divider is used, the path to drive the PLD logic array, local, or global clocks is not allowed. (3) There are four receiver PLLs in each transceiver block. Altera Corporation June 2006 IQ0 IQ1 Transmitter PLL /2 IQ2 ...

Page 42

... IQ2 Global Clks, I/O Bus, Gen Routing Receiver Transceiver Block 3 IQ0 IQ1 Global Clks, I/O Bus, Gen Routing TX PLL refclkb /2 IQ2 Global Clks, I/O Bus, Gen Routing Receiver Note ( PLLs ( PLLs PLD Global Clocks PLLs ( PLLs ( PLLS Altera Corporation June 2006 ...

Page 43

... Figure 2–28. EP1SGX25 Receiver PLL Recovered Clock to Regional Clock Connection In addition, the receiver PLL’s recovered clocks can drive fast regional lines (FCLK) as shown in their associated regions. Altera Corporation June 2006 2–31 show which fast regional and regional clock resource can be PLD Figure 2– ...

Page 44

... In the EP1SGX40 device, the receiver PLL recovered clocks from transceivers 0 and 1 drive RCLK[1..0] while transceivers 2, 3, and 4 drive RCLK[7..6]. The regional clocks feed logic in their associated regions. 2–34 Stratix GX Device Handbook, Volume 1 Stratix GX Transceiver Blocks PLD FCLK[1..0] Block 0 Block 1 Block 2 Block 3 FCLK[1..0] Altera Corporation June 2006 ...

Page 45

... Figure 2–30. EP1SGX40 Receiver PLL Recovered Clock to Regional Clock Connection Figure 2–31 regional clock resource. The fast regional clocks can drive logic in their associated regions. Altera Corporation June 2006 PLD shows the possible recovered clock connection to the fast Stratix GX Device Handbook, Volume 1 ...

Page 46

... Transmitter PLL Receiver PLL v GCLK v RCLK v FCLK 2–36 Stratix GX Device Handbook, Volume 1 PLD summarizes the possible clocking connections for the Destination Receiver GCLK RCLK PLL ( Stratix GX Transceiver Blocks FCLK[1..0] Block 0 Block 1 Block 4 Block 2 Block 3 FCLK[1..0] FCLK IQ Lines v ( Altera Corporation June 2006 ...

Page 47

... PLLs. The Stratix GX device can either globally power down and reset the transmitter and receiver channels or do each channel separately. connectivity between the reset signals and the Stratix GX logical blocks. Altera Corporation June 2006 Destination Receiver ...

Page 48

... PMOS resistors for I/O termination at the serial interface of receiver and transmitter channels (independent of power supply drift, process changes, or temperature variation) an external resistor, which is connected to the external low voltage power supply, is 2–38 Stratix GX Device Handbook, Volume Altera Corporation June 2006 ...

Page 49

... Stratix GX Example Application Support Stratix GX devices can be used for many applications, including: ■ ■ ■ Altera Corporation June 2006 Backplanes for traffic management and quality of service (QOS) Switch fabric applications for complete set for backplane and switch fabric transceivers Chip-to-chip applications such as: 10 Gigabit Ethernet XAUI to ...

Page 50

... Serial RapidIO PCI Express SMPTE 292M 2–40 Stratix GX Device Handbook, Volume 1 Bus Transfer Protocol 2.488 3.125 3.1875 2.5 1.0625, 2.125 1.25, 2.5, 3.125 ™ 2.5 1.485 Table 2–12 shows some of the Stratix GX (Gbps) (Supports up to 3.1875 Gbps) Altera Corporation June 2006 ...

Page 51

... The PLL can multiply the incoming low-frequency clock by a factor 10. The SERDES factor J can for the DPA mode for all other modes. The SERDES factor does not have to equal the clock Altera Corporation August 2005 3. Source-Synchronous Signaling With DPA Figure 3– ...

Page 52

... Figure shows the block diagram of a single SERDES receiver channel. shows the timing relationship between the data and clocks in × 10 mode the low-frequency multiplier and J × × × 3–1). The differential × W). Altera Corporation August 2005 ...

Page 53

... Receiver n – 1 data input Stratix GX Differential I/O Transmitter Operation You can configure any of the Stratix GX differential output channels as a transmitter channel. The differential transmitter serializes outbound parallel data. Altera Corporation August 2005 Source-Synchronous Signaling With DPA × 10 Mode Serial Shift Parallel ...

Page 54

... Transmitter Circuit Parallel Serial Register Register PD9 PD9 PD8 PD8 PD7 PD7 PD6 PD6 PD5 PD5 PD4 PD4 PD3 PD3 PD2 PD2 PD1 PD1 PD0 PD0 × W Fast TXLOADEN PLL n – mode the low-frequency TXOUT+ TXOUT− Altera Corporation August 2005 ...

Page 55

... Stratix GX source-synchronous circuitry with DPA. Figure 3–5. Source-Synchronous DPA Circuitry Receiver Circuit rx_in+ rx_in- rx_inclock_p rx_inclock_n Note to Figure 3–5: (1) Both deserializers are identical. The deserializer operation is described in the section. Altera Corporation August 2005 Source-Synchronous Signaling With DPA Deserializer (1) Dynamic Phase Aligner 8 Deserializer (1) ×W ×1 PLL ...

Page 56

... Table 3–2. I/O Standard Differential Input only Single ended Input only 20KE and APEX 20KC devices, With DPA 300 Mbps to 1 Gbps 717 MHz I/O banks 1 and 2 Dedicated inputs Receiver Pin Transmitter Pin Output only Input or output Altera Corporation August 2005 ...

Page 57

... I/O banks 1 and 2 of the device has one receiver channel and one transmitter channel per row. channels with DPA layout in EP1SGX10, EP1SGX25, and EP1SGX40 devices. In EP1SGX10 devices, only fast PLL 2 supports DPA operations. Altera Corporation August 2005 Source-Synchronous Signaling With DPA Receiver ...

Page 58

... Rows for 1 Transmitter 1 Receiver Figure 3–6: Fast PLL 1 in EP1SGX10 devices does not support DPA. Not all eight phases are used by the receiver channel or transmitter channel in non-DPA mode. 8 Fast PLL 1 (1) Eight-Phase Fast Clock PLL 2 8 Altera Corporation August 2005 ...

Page 59

... Figure 3–7. PLL & Channel Layout in EP1SGX40 Devices Notes to (1) (2) (3) Altera Corporation August 2005 Source-Synchronous Signaling With DPA CLKIN 1 Receiver 1 Transmitter 22 Rows 1 Transmitter 1 Receiver INCLK0 INCLK1 1 Receiver 1 Transmitter 23 Rows 1 Transmitter 1 Receiver CLKIN Figure 3–7: Corner PLLs do not support DPA. Not all eight phases are used by the receiver channel or transmitter channel in non-DPA mode ...

Page 60

... Stratix GX Device Handbook, Volume 1 3–1. Deserializer Synchronizer 10 10 Parallel Clock Figure 3–9 illustrates the clocks generated by the fast PLL Figure 3–8). “Principles of SERDES Stratix GX Logic Array Data Realigner GCLK RCLK Reset Altera Corporation August 2005 ...

Page 61

... At each rising edge of the clock, the dynamic phase selector determines the phase difference between the clock and the data and automatically compensates for the phase difference between the data and clock. Altera Corporation August 2005 Source-Synchronous Signaling With DPA D2 ...

Page 62

... Protocols Training Pattern Ten 0’s, ten 1’s ( 00000000001111111111 Four 0’s, four 1’s ( 00001111 two 0’s, one 1, four 0’s ( Eight alternating 1’s and 0’ 01010101 Not specified Table 3–4 are Number of Repetitions 256 ) ) or one 1, ) 10010000 10101010 or Figure 3–10. Altera Corporation August 2005 ...

Page 63

... Repeat this process until the realigner detects the desired match between the known data pattern and incoming parallel data pattern. Altera Corporation August 2005 Source-Synchronous Signaling With DPA Correct Alignment ...

Page 64

... D124 D113 D93 D113 D123 D112 D92 D112 D102 D111 D91 D111 D101 D110 D90 D110 D100 Nine bits slipped. 10 bits slipped. Counter = 9 Counter = 0 D119 is the upcoming Real data will resume bit to be slipped. on the next byte. Altera Corporation August 2005 ...

Page 65

... Altera Corporation August 2005 Source-Synchronous Signaling With DPA The design must include an input synchronizing register to ensure that data is synchronized to the ×W/J clock. After the state machine, use another synchronizing register to capture the generated rx_channel_data_align signal and synchronize it to the × ...

Page 66

... Introduction 3–16 Stratix GX Device Handbook, Volume 1 Altera Corporation August 2005 ...

Page 67

... LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, M512 RAM blocks, Altera Corporation February 2005 4. Stratix GX Architecture ® II Compiler places associated logic ® ...

Page 68

... LAB-wide clock signals. De-asserting the clock enable signal turns off the LAB-wide clock. 4–2 Stratix GX Device Handbook, Volume 1 shows the direct link connection. Local Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect to right LAB Altera Corporation February 2005 ...

Page 69

... A single LE also supports dynamic single bit addition or subtraction mode selectable by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and direct link interconnects. See Altera Corporation February 2005 labclkena2 labclkena1 labclk1 ...

Page 70

... Load and Chain ADATA Clear Logic ENA CLRN Register Feedback Carry-Out0 Carry-Out1 LAB Carry-Out Programmable Register LUT chain routing to next LE Row, column, and direct link Q routing Row, column, and direct link routing Local Routing Register chain output Altera Corporation February 2005 ...

Page 71

... LAB; and the register chain connection— are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset load, synchronous clear, synchronous load, and Altera Corporation February 2005 for more information on LUT chain and Normal mode ...

Page 72

... ENA 4-Input LUT clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide) Figure 4–5). The aload Row, column, and Q direct link routing Row, column, and direct link routing CLRN Local routing LUT chain connection Register chain output Altera Corporation February 2005 ...

Page 73

... LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor. Altera Corporation February 2005 4–6, the LAB carry-in signal selects either the carry-in0 or Stratix GX Device Handbook, Volume 1 Stratix GX Architecture 4– ...

Page 74

... Carry-Out1 shows the carry-select circuitry in an LAB for a 10-bit full aload (LAB Wide) ALD/PRE ADATA Row, column, and Q direct link routing D Row, column, and ENA direct link routing CLRN Local routing LUT chain connection Register chain output Altera Corporation February 2005 ...

Page 75

... The Quartus II Compiler creates carry chains longer than 10 LEs by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column. Altera Corporation February 2005 Stratix GX Architecture Stratix GX Device Handbook, Volume 1 ™ ...

Page 76

... An option set before compilation in the Quartus II software controls this pin. This chip-wide reset overrides all other control signals. 4–10 Stratix GX Device Handbook, Volume 1 LAB Carry-In Carry-In0 Carry-In1 LUT data1 data2 LUT LUT LUT Carry-Out0 Carry-Out1 Sum Altera Corporation February 2005 ...

Page 77

... For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive on to the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor Altera Corporation February 2005 Direct link interconnects between LABs and adjacent blocks. ...

Page 78

... Stratix GX Device Handbook, Volume 1 Adjacent LAB can C4, C8, and C16 Drive onto Another Column Interconnects (1) LAB's R4 Interconnect LAB Primary LAB Neighbor LAB (2) Neighbor Figure 4–8, with the exception that they connect to eight LABs R4 Interconnect Driving Right Altera Corporation February 2005 ...

Page 79

... LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. and register chain interconnects. Altera Corporation February 2005 LUT chain interconnects within an LAB Register chain interconnects within an LAB ...

Page 80

... Stratix GX Device Handbook, Volume 1 Local Interconnect Routing Among LEs in the LAB LE 1 LUT Chain Routing to Adjacent Local LE 3 Interconnect Figure 4–10 shows the C4 interconnect connections Register Chain Routing to Adjacent LE's Register Input Altera Corporation February 2005 ...

Page 81

... LAB. Every LAB has its own set of C8 interconnects to drive either up or down. C8 interconnect connections between the LABs in a column are similar to the C4 connections shown in exception that they connect to eight LABs above and below. The C8 Altera Corporation February 2005 Note (1) Local ...

Page 82

... These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[7..0]. 4–16 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 ...

Page 83

... Direct Link v Interconnect v R4 Interconnect v R8 Interconnect R24 Interconnect v C4 Interconnect v C8 Interconnect C16 Interconnect M512 RAM v Block v M4K RAM Block M-RAM Block v DSP Blocks Column IOE Row IOE Altera Corporation February 2005 shows the Stratix GX device’s routing scheme. Destination ...

Page 84

... M4K RAM Block (32 × 18 Bits) (128 × 36 Bits) (1) ( Outputs cleared Outputs cleared Input and output Input and output registers registers Unknown Unknown output/old data output/old data M-RAM Block (4K × 144 Bits Outputs unknown Output registers Unknown output Altera Corporation February 2005 ...

Page 85

... Figure 4–11. True Dual-Port Memory Configuration In addition to true dual-port memory, the memory blocks support simple dual-port and single-port RAM. Simple dual-port memory supports a simultaneous read and write and can either read old data before the write Altera Corporation February 2005 M512 RAM Block (32 × 18 Bits) ...

Page 86

... Figure 4–12: Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. rdaddress[ ] rden q[ ] outclock outclocken outaclr q[ ] outclock outclocken outaclr Altera Corporation February 2005 ...

Page 87

... The size × m × n shift register must be less than or equal to the maximum number of memory bits in the respective block: 576 bits for the M512 Altera Corporation February 2005 Stratix GX Architecture Stratix GX Device Handbook, Volume 1 ...

Page 88

... M4K blocks provide additional resources for channelized functions that do not require large amounts of storage. The M-RAM blocks provide a large 4–22 Stratix GX Device Handbook, Volume 1 Figure 4–13 shows the Number of Taps w w Altera Corporation February 2005 ...

Page 89

... M512 RAM block configurations. Table 4–3. M512 RAM Block Configurations (Simple Dual-Port RAM) Read Port 512 256 128 Altera Corporation February 2005 Simple dual-port RAM Single-port RAM FIFO ROM Shift register 512 × 1 256 × 2 128 × ...

Page 90

... LABs on either its left or right side. RAM block to logic array interface. 4–24 Stratix GX Device Handbook, Volume 1 “I/O Structure” on page 4–96 for details on dedicated Figure 4–14 shows the M512 RAM block Figure 4–15 shows the M512 Altera Corporation February 2005 ...

Page 91

... Figure 4–14. M512 RAM Block Control Signals Dedicated Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Altera Corporation February 2005 8 outclocken inclocken inclock outclock Stratix GX Architecture wren outclr rden inclr Stratix GX Device Handbook, Volume 1 4–25 ...

Page 92

... M512 RAM Block Control Signals datain address Clocks 2 LAB Row Clocks True dual-port RAM Simple dual-port RAM Single-port RAM FIFO ROM Shift register R4 and R8 Interconnects Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB Altera Corporation February 2005 ...

Page 93

... When the M4K RAM block is configured as a shift register block, you can create a shift register up to 4,608 bits (w × m × n). Altera Corporation February 2005 Tables 4–4 and 4–5 summarize the possible M4K RAM block Write Port 1K ° 4 512 ° 8 256 ° 16 128 ° ...

Page 94

... Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, that is, in ×16 and ×32 modes. Figure summarizes the byte Notes (1), (2) datain ×36 [8..0] [17..9] – [26..18] – [35..27] 4–16. Figure 4–17 shows Altera Corporation February 2005 ...

Page 95

... Figure 4–17. M4K RAM Block LAB Row Interface C4 and C8 Interconnects 10 Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB M4K RAM Block Local Interconnect Region Altera Corporation February 2005 clocken_a alcr_a renwe_b renwe_a alcr_b dataout M4K RAM Block Byte enable Control ...

Page 96

... Stratix GX Device Handbook, Volume 1 True dual-port RAM Simple dual-port RAM Single-port RAM FIFO RAM Tables 4–7 64K × 9 32K × × × × × 72 × 144 and 4–8 summarize the Write Port 16K × × × 144 Altera Corporation February 2005 ...

Page 97

... The byte enables are available for the ×18, ×36, and ×72 modes. In the ×144 simple dual-port mode, the two sets of byteena signals (byteena_a and byteena_b) are combined to form the necessary 16 byte enables. Table 4–9. Byte Enable for M-RAM Blocks byteena[3..0] Altera Corporation February 2005 Port A 64K × × ...

Page 98

... Byte enables can be used in the same manner with 8-bit words, that is, in ×16, ×32, ×64, and ×128 modes. Figure Notes (1), (2) datain ×144 [8..0] [17..9] [26..18] [35..27] [44..36] [53..45] [62..54] [71..63] [80..72] [89..81] [98..90] [107..99] [116..108] [125..117] [134..126] [143..135] 4–18. Altera Corporation February 2005 ...

Page 99

... B, and the bottom side has another 72 data inputs and 72 data outputs for port A. shows an example floorplan for the EP1SGX40 device and the location of the M-RAM interfaces. Altera Corporation February 2005 8 clocken_a clocken_b ...

Page 100

... M-RAM block are possible from the left adjacent LABs for M-RAM 4–34 Stratix GX Device Handbook, Volume 1 Note (1) Independent M-RAM blocks interface to top, bottom, and side facing device perimeter for easy access to horizontal I/O pins. M-RAM M-RAM Block Block M-RAM M-RAM Block Block LABs DSP Blocks Altera Corporation February 2005 ...

Page 101

... LABs for M-RAM blocks facing to the right. For column interfacing, every M-RAM column unit connects to the right and left column lines, allowing each M-RAM column unit to communicate directly with three columns of LABs. block and the logic array. Altera Corporation February 2005 Figures 4–20 through 4–22 ...

Page 102

... Notes (1), M512 RAM Block Columns Port B M-RAM Block Port (2) LABs in Column M-RAM Boundary Column Interface Block Drives to and from C4 and C8 Interconnects B5 B6 Column Interface Block A5 A6 Allows LAB Columns to Drive datain and dataout to and from M-RAM Block Altera Corporation February 2005 ...

Page 103

... Figure 4–21. M-RAM Row Unit Interface to Interconnect Direct Link Interconnects Altera Corporation February 2005 C4 and C8 Interconnects R4 and R8 Interconnects LAB Row Interface Block M-RAM Block to LAB Row Interface Block Interconnect Region Stratix GX Device Handbook, Volume 1 Stratix GX Architecture M-RAM Block addressa addressb renwe_a ...

Page 104

... TriMatrix Memory Figure 4–22. M-RAM Column Unit Interface to Interconnect 4–38 Stratix GX Device Handbook, Volume 1 C4 and C8 Interconnects LAB LAB 12 datain M-RAM Block LAB M-RAM Block to LAB Row Interface Block Interconnect Region Column Interface Block 12 dataout Altera Corporation February 2005 ...

Page 105

... B6 and A1 to A6). It also shows the address and control signal input connections to the row units (R1 to R11). Table 4–11. M-RAM Row & Column Interface Unit Signals Unit Interface Block Altera Corporation February 2005 shows the input and output data signal connections for the Input SIgnals R1 addressa[7 ...

Page 106

... B controls all registers on the port B side. Each port, A and B, also supports independent clock enables and asynchronous clear signals for port A and B registers. independent clock mode. 4–40 Stratix GX Device Handbook, Volume 1 Figure 4–23 shows a TriMatrix memory block in Altera Corporation February 2005 ...

Page 107

... Figure 4–23. Independent Clock Mode Note to (1) Altera Corporation February 2005 Figure 4–23: All registers shown have asynchronous clear ports. Stratix GX Architecture Note (1) Stratix GX Device Handbook, Volume 1 4–41 ...

Page 108

... The other clock controls the block’s data output registers. Each memory block port also supports independent clock enables and asynchronous clear signals for input and output registers. clock mode. 4–42 Stratix GX Device Handbook, Volume 1 Figures 4–24 and 4–25 show the memory block in input/output Altera Corporation February 2005 ...

Page 109

... Figure 4–24. Input/Output Clock Mode in True Dual-Port Mode Note to (1) Altera Corporation February 2005 Figure 4–24: All registers shown have asynchronous clear ports. Stratix GX Architecture Note (1) Stratix GX Device Handbook, Volume 1 4–43 ...

Page 110

... D Q Read Address ENA Data Out Byte Enable D Q ENA Write Address D Q ENA Read Enable D Q ENA D Q Write Write Enable Pulse ENA Generator To MultiTrack Interconnect D Q ENA Figure 4–26 shows a Altera Corporation February 2005 ...

Page 111

... See block in a memory block can support up to two single-port mode RAM blocks in the M4K RAM blocks if each RAM block is less than or equal to 2K bits in size. Altera Corporation February 2005 Note (1) Memory Block 256 × 16 512 × ...

Page 112

... ENA 4,096 × 1 Data Out D Q Address ENA Write Enable D Q Write ENA Pulse Generator Eight 9 × 9-bit multipliers Four 18 × 18-bit multipliers One 36 × 36-bit multiplier 512 × MultiTrack Interconnect D Q ENA Table 4–12). Altera Corporation February 2005 ...

Page 113

... The following list provides the largest functions that can fit into a single DSP block. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 1 Figure 4–28 Altera Corporation February 2005 36 36-bit unsigned by unsigned multiplication × 36 36-bit signed by signed multiplication × 35 36-bit unsigned by signed multiplication × 36 35-bit signed by unsigned multiplication × ...

Page 114

... Digital Signal Processing Block Figure 4–28. DSP Blocks Arranged in Columns 4–48 Stratix GX Device Handbook, Volume 1 DSP Block Column DSP Block 8 LAB Rows Altera Corporation February 2005 ...

Page 115

... DSP block. Additionally, the DSP block input registers can efficiently implement shift registers for FIR filter applications. Figure 4–29 18 × configuration of the DSP block. Altera Corporation February 2005 shows the number of DSP blocks in each Stratix GX device. Total 9 Device DSP Blocks Multipliers ...

Page 116

... Summation Stage ENA for Adding Four CLRN Multipliers Together Adder/ Subtractor/ Accumulator Optional Pipeline ENA Register Stage CLRN Optional Input Register Stage with Parallel Input or Shift Register Configuration Output Selection Multiplexer Summation Optional Output Register Stage to MultiTrack Interconnect Altera Corporation February 2005 ...

Page 117

... Figure 4–30. DSP Block Diagram for 9 Altera Corporation February 2005 9-Bit Configuration × ENA CLRN D Q ENA CLRN D Q ENA CLRN Adder/ Subtractor ENA CLRN D Q ENA CLRN D Q ENA CLRN D Q ENA CLRN D Q ENA CLRN D Q ENA CLRN Adder/ ...

Page 118

... These signals can be unregistered or registered once to match data path pipelines if required. 4–52 Stratix GX Device Handbook, Volume 1 Multiplier block Adder/output block sign_a (1) sign_b (1) aclr[3..0] clock[3..0] ena[3..0] shiftin ENA CLRN CLRN D Q CLRN Figure 4–31. Result to Adder Q blocks Optional Multiply-Accumulate and Multiply-Add Pipeline Altera Corporation February 2005 ...

Page 119

... LAB LEs. You implement all the filter circuitry within the DSP block and its routing resources, saving LE and general routing resources for general logic. External registers are needed for shift register inputs when using 36 Altera Corporation February 2005 36-bit multipliers. × ...

Page 120

... ENA D Q CLRN ENA CLRN D Q ENA D Q CLRN ENA D Q CLRN ENA CLRN D Q ENA D Q CLRN ENA D Q CLRN ENA CLRN Note (1) A[n] × B[n] A[n Ð 1] × B[n Ð 1] A[n Ð 2] × B[n Ð 2] Altera Corporation February 2005 ...

Page 121

... Table 4–14. Multiplier Signed Representation Altera Corporation February 2005 shows the summary of input register modes for the DSP block × ...

Page 122

... The system cannot use adder/output blocks independently of the multiplier. 4–56 Stratix GX Device Handbook, Volume 18-bit multipliers can optionally feed a register × × 36-bit multipliers, this register pipelines the multiplier function. × Figure 4–33 shows the adder and output stages. Altera Corporation February 2005 ...

Page 123

... Notes to Figure 4–33: (1) Adder/output block shown in Figure 4–33 blocks and two summation blocks. (2) These signals are either not registered, registered once, or registered twice to match the data path pipeline. Altera Corporation February 2005 Note (1) Accumulator Feedback Adder/ Subtractor/ Summation Adder/ Subtractor/ Accumulator Feedback × ...

Page 124

... Stratix GX Device Handbook, Volume 1 18-bit mode. There are two addnsub[1..0] signals × Figure 4–33. The 9-bit mode, there are two summation blocks providing × 9-bit multipliers × 9-bit mode, one × 18-bit mode, there × 18-bit × Altera Corporation February 2005 ...

Page 125

... Simple Multiplier Mode In simple multiplier mode, the DSP block drives the multiplier sub-block result directly to the output with or without an output register four 18 × directly out of one DSP block. See Altera Corporation February 2005 Simple multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder Each DSP block can only support one mode. Mixed modes in the same DSP block is not supported ...

Page 126

... ENA CLRN 18-bit multipliers combined with × 36-bit multiplier 36-bit mode, the device can use the register × 36-bit multiplier. Figure 4–35 × Data Out D Q ENA CLRN 36-bit multiplier in multiplier × shows the 36 36-bit multiply × Altera Corporation February 2005 ...

Page 127

... D Q ENA CLRN Notes to Figure 4–35: (1) These signals are not registered or registered once to match the pipeline. (2) These signals are not registered, registered once, or registered twice for latency to match the pipeline. Altera Corporation February 2005 D Q ENA CLRN D Q ENA 36 × 36 Multiplier ...

Page 128

... DSP block. The first and third multiplier sub- × ENA CLRN addnsub (2) signa (2) signb (2) accum_sload (2) 18-bit multipliers each or four sums or differences from two 9 Figure 4–36), the DSP block drives D Q Data Out ENA Accumulator CLRN overflow × Altera Corporation February 2005 9-bit ...

Page 129

... DSP block. The product width for each multiplier must be the same size. The four-multipliers adder mode is useful for FIR filter applications. adder mode. Altera Corporation February 2005 ( jd) = [(a c) – (b × ...

Page 130

... These signals are not registered, registered once, or registered twice for latency to match the data path pipeline. 4–64 Stratix GX Device Handbook, Volume ENA Adder/Subtractor CLRN D Q addnsub1 (2) ENA Summation signa (2) signb (2) CLRN addnsub3 ( ENA Adder/Subtractor CLRN D Q ENA CLRN Data Out D Q ENA CLRN Altera Corporation February 2005 ...

Page 131

... LEs. If the DSP block is configured as 36 accumulator stages are implemented in LEs. Each DSP block can route the shift register chain out of the block to cascade two full columns of DSP blocks. Altera Corporation February 2005 shows the different number of multipliers possible in each 9 9 ...

Page 132

... A local × 4–40 show the DSP block interfaces to LAB rows. DSP Block OA[17..0] MultiTrack Interconnect A1[17..0] OB[17..0] B1[17..0] OC[17..0] A2[17..0] OD[17..0] B2[17..0] OE[17..0] A3[17..0] OF[17..0] B3[17..0] OG[17..0] A4[17..0] OH[17..0] B4[17..0] Figures 4–39 MultiTrack Interconnect Altera Corporation February 2005 ...

Page 133

... A bus of 18 control signals feeds the entire DSP block. These signals include clock[0..3] clocks, aclr[0..3] asynchronous clears, ena[1..4] clock enables, signa, signb signed/unsigned control signals, addnsub1 and addnsub3 addition and subtraction control signals, and accum_sload[0..1] accumulator synchronous loads. The Altera Corporation February 2005 R4 and R8 Interconnects DSP Block Row Structure ...

Page 134

... A1[17..0] aclr0 B1[17..0] accum_sload0 addnsub1 A2[17..0] clock0 ena0 aclr1 B2[17..0] clock1 ena1 aclr2 A3[17..0] clock2 ena2 sign_b B3[17..0] clock3 ena3 clear3 A4[17..0] accum_sload1 addnsub3 B4[17..0] Table 4–16. Data Outputs OA[17..0] OB[17..0] OC[17..0] OD[17..0] OE[17..0] OF[17..0] OG[17..0] OH[17..0] Altera Corporation February 2005 ...

Page 135

... The global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. 12 dedicated CLK pins and the transceiver clocks driving global clock networks. Altera Corporation February 2005 Stratix GX Architecture Figure 4–41. ...

Page 136

... The regional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant. The CLK clock pins symmetrically drive the RCLK networks within a particular quadrant, as shown in 4–70 Stratix GX Device Handbook, Volume 1 CLK[15..12] Global Clock [15..0] CLK[7..4] Figure 4–42. Transceiver Clocks Altera Corporation February 2005 ...

Page 137

... All devices have eight FCLK pins to drive fast regional clock networks. Any I/O pin can drive a clock or control signal onto any fast regional clock network with the addition of a delay. The I/O interconnect drives this signal. Altera Corporation February 2005 RCLK[15..14] CLK[3..0] CLK[7 ...

Page 138

... PLLs & Clock Networks Figure 4–43. EP1SGX25 & EP1SGX10 Device Fast Clock Pin Connections to Fast Regional Clocks 4–72 Stratix GX Device Handbook, Volume 1 Fast Clock Fast Clock [3..2] FCLK[1..0] FCLK[1..0] [5..4] Fast Clock Fast Clock [1..0] FCLK[1..0] FCLK[1..0] [7..6] Altera Corporation February 2005 ...

Page 139

... Multiplexers are used with these clocks to form 8-bit busses to drive LAB row clocks, column IOE clocks, or row IOE clocks. Another multiplexer at the LAB level selects two of the eight row clocks to feed the LE registers within the LAB. See Altera Corporation February 2005 Fast Clock Fast Clock ...

Page 140

... Stratix GX Device Handbook, Volume 1 Clocks Available to a Quadrant or Half-Quadrant Clock [21:0] Figures 4–46 and 4–47 show the quadrant and half- Vertical I/O Cell IO_CLK[7..0] Lab Row Clock [7..0] Horizontal I/O Cell IO_CLK[7..0] Altera Corporation February 2005 ...

Page 141

... Figure 4–46. EP1SGX25 & EP1SGX10 Device I/O Clock Groups 8 IO_CLKH[7:0] 8 IO_CLKG[7:0] 8 Altera Corporation February 2005 IO_CLKA[7:0] IO_CLKB[7: Clocks in the Quadrant 22 Clocks in the Quadrant 8 IO_CLKF[7:0] IO_CLKE[7:0] Stratix GX Device Handbook, Volume 1 Stratix GX Architecture 8 I/O Clock Regions 13 22 Clocks in the Quadrant Clocks in the Quadrant 15 4– ...

Page 142

... With features such as clock switchover, spread spectrum 4–76 Stratix GX Device Handbook, Volume 1 IO_CLKB[7:0] IO_CLKC[7: Clocks in the 22 Clocks in the Half-Quadrant Half-Quadrant 22 Clocks in the 22 Clocks in the Half-Quadrant Half-Quadrant 8 8 IO_CLKK[7:0] IO_CLKJ[7:0] IO_CLKD[7: I/O Clock Regions 13 22 Clocks in the Half-Quadrant Clocks in the Half-Quadrant 15 8 IO_CLKI[7:0] Altera Corporation February 2005 ...

Page 143

... Table 4–18. Stratix GX Enhanced PLL & Fast PLL Features (Part Feature Clock multiplication and division Phase shift Delay shift Clock switchover PLL reconfiguration Programmable bandwidth Spread spectrum clocking Programmable duty cycle Number of internal clock outputs Altera Corporation February 2005 Table 4–17 Fast PLLs 4 ( (1) 10 ...

Page 144

... Every Stratix GX device has two enhanced PLLs with one single-ended or differential external feedback input per PLL. Figure 4–48 PLL floorplan. 4–78 Stratix GX Device Handbook, Volume 1 Enhanced PLL Four differential/eight singled-ended or one single-ended (6) (8) 4 shows a top-level diagram of the Stratix GX device and the Notes (1)–(8) Fast PLL (7) Altera Corporation February 2005 ...

Page 145

... Figure 4–48. PLL Floorplan 7 FPLL7CLK 1 CLK[3..0] 2 PLLs FPLL8CLK 8 Figure 4–49 PLL outputs and the CLK pins. Altera Corporation February 2005 CLK[15..12 CLK[7..4] shows the global and regional clock connections from the Stratix GX Device Handbook, Volume 1 Stratix GX Architecture High-Speed Transceivers inclk1 ...

Page 146

... PLLs 1,2 7, and 8 are fast PLLs. PLLs 7 and 8 do not drive global clocks. Figure 4–50 outputs and top CLK pins. 4–80 Stratix GX Device Handbook, Volume PLL PLL PLL PLL Regional Clocks shows the global and regional clocking from enhanced PLL Note (1) Global Clocks Altera Corporation February 2005 ...

Page 147

... Figure 4–50. Global & Regional Clock Connections From Top Clock Pins & Enhanced PLL Outputs Regional RCLK2 Clocks RCLK3 Global Clocks RCLK6 Regional Clocks RCLK7 Note to Figure 4–50: (1) PLLs 5, 6, 11, and 12 are enhanced PLLs. Altera Corporation February 2005 (1) (2) (1) E[0..3] PLL 5 PLL 11 ( PLL 6 PLL 12 (4) (1) (1) ...

Page 148

... VCO Phase Selection Affecting All Outputs shows a diagram of the Programmable Time Delay on Each PLL Port Δt /l0 Regional Clocks Δt /l1 4 Δt Global /g0 Clocks Δt /g1 Δt /g2 I/O Buffers (2) Δt /g3 to I/O or general routing Δt /e0 Δt /e1 4 Δt /e2 Δt /e3 I/O Buffers (3) Altera Corporation February 2005 ...

Page 149

... Clock-sense circuitry automatically switches from the primary to secondary clock for PLL reference when the primary clock signal is not present. Altera Corporation February 2005 Figure 4–52 shows a block diagram of the switchover Stratix GX Device Handbook, Volume 1 Stratix GX Architecture × ...

Page 150

... This feature is useful when clock sources can originate from multiple cards on the backplane, CLK0_BAD CLK1_BAD Active Clock CLKLOSS CLKSWITCH Δt PFD FBCLK Figure 4–52. In this case, Altera Corporation February 2005 ...

Page 151

... PLL using a input shift clock rate of 25 MHz. The charge pump, loop filter components, and phase shifting using VCO phase taps cannot be dynamically adjusted. Altera Corporation February 2005 requiring a system-controlled switchover between frequencies of operation. You can use clkswitch together with the lock signal to trigger the switch from a clock that is running but becomes unstable and cannot be locked onto ...

Page 152

... Bandwidth is programmable from 150 kHz to 2 MHz. 4–86 Stratix GX Device Handbook, Volume 1 Charge Loop PFD VCO Pump Filter Δt ÷m All Output Counters and Clock Delay Settings can be Programmed Dynamically Δt ÷g Δt ÷l Δt ÷e Altera Corporation February 2005 ...

Page 153

... Any of the four external output counters can drive the single-ended or differential clock outputs for PLLs 5 and 6. This means one counter or frequency can drive all output pins available from PLL 5 or PLL 6. Each Altera Corporation February 2005 From IOE (1) From IOE (1) From IOE (1) ...

Page 154

... Differential SSTL 3.3-V GTL 3.3-V GTL+ 1.5-V HSTL class I 1.5-V HSTL class II SSTL-18 class I SSTL-18 class II SSTL-2 class I SSTL-2 class II 4–88 Stratix GX Device Handbook, Volume 1 Input INCLK FBIN Table 4–19 shows which I/O Output PLLENABLE EXTCLK Altera Corporation February 2005 ...

Page 155

... I/O pin as an external output clock. The jitter on the output clock is not guaranteed for these cases. Clock Feedback The following four feedback modes in Stratix GX device enhanced PLLs allow multiplication and/or phase and delay shifting: ■ ■ Altera Corporation February 2005 Input INCLK FBIN ...

Page 156

... You define which internal clock output from the PLL should be phase-aligned to the internal clock pin. No compensation: In this mode, the PLL does not compensate for any clock networks or external clock outputs. Altera Corporation February 2005 ...

Page 157

... PLLs relock and resynchronize to the input clocks. You can choose which PLLs are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. Altera Corporation February 2005 Stratix GX Architecture Stratix GX Device Handbook, Volume 1 4–91 ...

Page 158

... PLL does not need a resynchronization or relock period 4–92 Stratix GX Device Handbook, Volume 1 PLL Reconfiguration or Clock switchover enables in the design. Phase relationships between output clocks need to be maintained after a loss of lock condition Figure 4–56 shows the Altera Corporation February 2005 ...

Page 159

... COUNTER OUTPUT CLKENA CLKOUT Fast PLLs Stratix GX devices contain up to four fast PLLs with high-speed serial interfacing ability, along with general-purpose features. shows a diagram of the fast PLL. Altera Corporation February 2005 Stratix GX Architecture Figure 4–57 Stratix GX Device Handbook, Volume 1 4–93 ...

Page 160

... Stratix GX Device Handbook, Volume 1 VCO Phase Selection Selectable at each PLL Output Port 8 Charge Loop VCO Pump Filter ÷ m Post-Scale Counters diffioclk1 (2) Global or ÷l0 regional clock txload_en rxload_en ÷l1 Global or regional clock diffioclk2 (2) Global or ÷g0 regional clock Altera Corporation February 2005 ...

Page 161

... SSTL-18 class I SSTL-18 class II SSTL-2 class I SSTL-2 class II SSTL-3 class I SSTL-3 class II AGP (1× and 2× ) CTT Altera Corporation February 2005 shows the I/O standards supported by fast PLL input pins. I/O Standard Stratix GX Device Handbook, Volume 1 Stratix GX Architecture Input INCLK PLLENABLE ...

Page 162

... Programmable pull-up during configuration Output drive strength control Slew-rate control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Programmable input and output delays Open-drain outputs DQ and DQS I/O pins Double-data rate (DDR) Registers Figure 4–58 shows the Stratix GX IOE structure. The Altera Corporation February 2005 ...

Page 163

... There are up to four IOEs per row I/O block and six IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 4–59 Figure 4–60 Altera Corporation February 2005 OE Register D Q ...

Page 164

... I/O Interconnect Interconnects I/O Block Local Interconnect from I/O Interconnect ( io_dataouta[3..0] io_dataoutb[3..0] Direct Link Interconnect to Adjacent LAB io_clk[7:0] 16 Control Signals 28 Data & Control Signals from Logic Array (2) Horizontal I/O Block Horizontal I/O Block Contains up to Four IOEs Altera Corporation February 2005 ...

Page 165

... The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear signals io_cclr[5..0]. Altera Corporation February 2005 Vertical I/O Block 16 ...

Page 166

... Stratix GX Device Handbook, Volume 1 4–68). To Other IOEs oe ce_in ce_out Control aclr/preset Signal Selection sclr clk_in clk_out Figure 4–62 illustrates the control signal Figure 4–61 illustrates the IOE Altera Corporation February 2005 ...

Page 167

... The OE and output register share the same clock source and the same clock enable source from local interconnect in the associated LAB, dedicated I/O clocks, and the column and row interconnects. shows the IOE in bidirectional configuration. Altera Corporation February 2005 io_bclk[3..0] io_bce[3..0] ...

Page 168

... Logic Array Delay Input Register Delay Input Register D Q Input Clock ENA Enable Delay CLRN/PRN Output t Delay ZX OE Register t Delay CO V CCIO Optional PCI Clamp V CCIO Programmable Pull-Up Resistor Slew Control Input Pin to Bus-Hold Input Pin to Circuit Altera Corporation February 2005 ...

Page 169

... Stratix GX devices have six registers in the IOE, which support DDR interfacing by clocking data on both positive and negative clock edges. The IOEs in Stratix GX devices support DDR inputs, DDR outputs, and bidirectional DDR modes. Altera Corporation February 2005 delay to the output pin, which is required for ZBT interfaces. ZX shows the programmable delays for Stratix GX devices ...

Page 170

... Input Register Delay Input Register D Q ENA CLRN/PRN Output Clock Enable Delay Chip-Wide Reset Input Register D Q ENA CLRN/PRN Figure 4–65 shows VCCIO Optional PCI Clamp To DQS Local Bus (3) VCCIO Programmable Pull-Up Resistor Bus-Hold Circuit Latch D Q ENA CLRN/PRN Altera Corporation February 2005 ...

Page 171

... One output register clocks the first bit out on the clock high time, × while the other output register clocks the second bit out on the clock low time. shows the DDR output timing diagram. Altera Corporation February 2005 ...

Page 172

... D Q Register Delay ENA CLRN/PRN (1), (2) Output t Delay ZX OE Register t Delay CO V CCIO Optional PCI Clamp V CCIO Programmable Pull-Up Used for Resistor DDR SDRAM Output Pin Delay clk Drive Strength Control Open-Drain Output Slew Control Bus-Hold Circuit Altera Corporation February 2005 ...

Page 173

... To find out more about the DDR SDRAM specification, see the JEDEC web site (www.jedec.org). For information on memory controller megafunctions for Stratix GX devices, see the Altera web site (www.altera.com). See AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices for more information on DDR SDRAM interface in Stratix GX. Also see AN 349: QDR SRAM Controller Reference Design for Stratix & ...

Page 174

... Maximum Clock Rate (MHz) I/O Standard -5 Speed Grade -6 Speed Grade SSTL-2 200 SSTL-2 150 1.8-V HSTL 200 1.5-V HSTL 167 1.5-V HSTL 200 LVTTL 200 -7 Speed Grade 167 133 133 133 (5) (5) 167 133 167 133 200 167 Altera Corporation February 2005 ...

Page 175

... DQS delay elements. control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device. Altera Corporation February 2005 shows the number of DQ and DQS buses that are supported Note (1) Number of × ...

Page 176

... GTL+ support a minimum setting, the lowest drive strength that guarantees the I provides signal slew rate control to reduce system noise and signal overshoot. 4–110 Stratix GX Device Handbook, Volume 1 Phase Up/Down Comparator Counter Delay Chains the standard. Using minimum settings OH OL Control Signals to DQS Pins Altera Corporation February 2005 ...

Page 177

... Compliant” for 3.3-V PCI, 3.3-V PCI-X 1.0, and Compact PCI I/O standards. Stratix GX devices support series on-chip termination (OCT) using programmable drive strength. For more information, contact your Altera Support Representative. Open-Drain Output Stratix GX devices provide an optional open-drain (equivalent to an open-collector) output for each I/O pin ...

Page 178

... GTL+ I/O standard or when the I/O pin has been configured for differential signals. 4–112 Stratix GX Device Handbook, Volume 1 shows bus hold support for different pin types. Pin Type CCIO Bus Hold prevent overdriving Altera Corporation February 2005 ...

Page 179

... Advanced I/O Standard Support Stratix GX device IOEs support the following I/O standards: ■ ■ ■ ■ ■ ■ ■ ■ Altera Corporation February 2005 Table 4–26 Pin Type Table 4–26: TDO pins do not support programmable weak pull-up resistors. LVTTL LVCMOS 1 ...

Page 180

... N/A 3.3 N/A 2.5 N/A 1.8 N/A 1.5 N/A 3.3 N/A 3.3 N/A 3.3 N/A 3.3 N/A 3.3 N/A 2.5 N/A 1.5 0.75 2.5 1.25 N/A 1.20 N/A 1.5 1.5 0.75 1.8 0.9 1.8 0.90 2.5 1.25 Altera Corporation February 2005 ...

Page 181

... SSTL-18 Class II, and HSTL Class II outputs. The top and bottom I/O banks support all single-ended I/O standards. Additionally, Stratix GX devices support four enhanced PLL external clock output banks, allowing clock output capabilities such as differential support for SSTL and HSTL. Altera Corporation February 2005 Input Reference Voltage (V ) ...

Page 182

... PCML (5) I/O Banks & 12 Support All Single-Ended I/O Standards ( Bank 7 PLL12 VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7 PLL6 DQSB4 DQSB3 DQSB2 DQST1 DQST0 Bank 4 I/O Bank 13 I/O Bank 14 I/O Bank 17 I/O Bank 16 I/O Bank 15 DQSB1 DQSB0 Altera Corporation February 2005 (5) (5) (5) (5) (5) ...

Page 183

... GTL 3.3-V GTL+ 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II SSTL-18 class I SSTL-18 class II SSTL-2 class I SSTL-2 class II SSTL-3 class I Altera Corporation February 2005 shows I/O standard support for each I/O bank. Left Banks ( & & ...

Page 184

... LVPECL signals require an external termination resistor. shows the device with differential termination. 4–118 Stratix GX Device Handbook, Volume 1 Left Banks ( & & CCIO Enhanced PLL External Clock Output Banks (9, 10, 11 & 12 for CCIO is 3 bank can support Figure 4–70 Altera Corporation February 2005 ...

Page 185

... Table 4–30 Table 4–30. Differential Termination Support Across Pin Types Top and bottom I/O banks ( and 8) DIFFIO_RX[] CLK[0,2,9,11],CLK[4-7],CLK[12-15] CLK[1,3,8,10] FCLK FPLL[7..10]CLK The differential on-chip resistance at the receiver input buffer is 118 Altera Corporation February 2005 Transmitting Device Ð shows the Stratix GX device differential termination support. ...

Page 186

... CCIO level, input pins are 1.5-V, 1.8-V, 2.5-V, and CCINT Figure 4–71. This ) D LVDS Input Buffer Differential On-Chip Termination Resistor Resistance Unit Min Typ Max Ω 110 135 165 Ω 100 135 170 = 100 C, j Altera Corporation February 2005 ...

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... Once operating conditions are reached and the device is configured, Stratix GX devices operate as specified by the user. For more information, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2. Altera Corporation February 2005 summarizes Stratix GX MultiVolt I/O support. Note (1) ...

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... I/O pins. 4–122 Stratix GX Device Handbook, Volume 1 ® embedded logic analyzer. Stratix GX Description ® embedded logic analyzer. register and places it between the TDI and TDO pins, USERCODE to be serially shifted out of TDO. USERCODE Table 4–33. Altera Corporation February 2005 ...

Page 189

... Table 4–34. Stratix GX Boundary-Scan Register Length Table 4–35. 32-Bit Stratix GX Device IDCODE (Part Device Version (4 Bits) EP1SGX10 0000 EP1SGX25 0000 Altera Corporation February 2005 Description download cable, or when using a TM pin low to trigger reconfiguration even though the physical nCONFIG Device EP1SGX10 ...

Page 190

... JTAG timing parameters and values for Stratix GX Parameter clock period TCK TCK clock high time clock low time TCK JTAG port setup time (1) LSB (1 Bit) (11 Bits) 000 0110 1110 JPSU JPH t JPXZ t JSXZ Min (ns) Max (ns) 100 Altera Corporation February 2005 (2) ...

Page 191

... Altera Corporation February 2005 Parameter JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output ...

Page 192

... IEEE Std. 1149.1 (JTAG) Boundary-Scan Support 4–126 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 ...

Page 193

... Stratix GX devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable configuration devices that configure Stratix GX devices via a serial data stream. ...

Page 194

... Enhanced or EPC2 configuration device ByteBlasterMV™ or MasterBlaster™ download cable or serial data source Parallel data source Parallel data source MasterBlaster or ByteBlasterMV download cable or a microprocessor with a Jam or JBC file (.jam or .jbc) before CCIO 5–1), chosen on the basis of the Data Source Altera Corporation February 2005 ...

Page 195

... Stratix GX Architecture chapter of the Stratix GX Device Handbook, Volume 1 for more information on Stratix GX PLLs. Remote Update Configuration Modes Stratix GX devices also support remote configuration using an Altera enhanced configuration device (for example, EPC16, EPC8, and EPC4 devices) with page mode selection. Factory configuration data is stored in the default page of the configuration device ...

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... Determines whether to enable a user watchdog timer for the application configuration Determines what the watchdog timer setting should enabled ® embedded processor, can help the Stratix GX device determine Figure 5–1 shows the Stratix GX remote update. shows the transition diagram for remote update mode. Altera Corporation February 2005 ...

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... Note to Figure 5–1: (1) When the Stratix GX device is configured with the factory configuration, it can handle update data from EPC16, EPC8, or EPC4 configuration device pages and point to the next page in the configuration device. Altera Corporation February 2005 Configuration Device (1) Application Configuration Application Configuration ...

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... Remote update of application configuration is controlled by a Nios embedded processor or user logic programmed in the factory or application configurations. ( seven pages can be specified allowing up to seven different configuration applications. 5–6 Stratix GX Device Handbook, Volume 1 Notes (1), (2) Power-Up Configuration Error Factory Configuration Configuration Error Application 1 Configuration Reload an Application Reload an Application Application n Configuration Altera Corporation February 2005 ...

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... Device & Pin Options dialog box in the Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of Detection the best options for mitigating SEU. Altera Corporation February 2005 shows the transition diagram for local update mode. Power-Up or nCONFIG ...

Page 200

... CRC circuitry verifies the internal configuration SRAM bits in the FPGA device. For more information on CRC, refer to AN 357: Error Detection Using CRC in Altera FPGA Devices. Temperature- Stratix GX devices include a diode-connected transistor for use as a temperature sensor in power management. This diode is used with an ...

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