EP2S90F1020C5N Altera, EP2S90F1020C5N Datasheet - Page 128

• Manufacturer Part Number: EP2S90F1020C5N
• Description: IC STRATIX II FPGA 90K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S90F1020C5N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520488
• Number Of I /o: 758
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 758
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520488
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1918; EP2S90F1020C5N

Document Revision History
Document
Revision History
3–14
Stratix II Device Handbook, Volume 1
May 2007, v4.2 Moved Document Revision History section to the end
Table 3–7. Document Revision History (Part 1 of 2)
Document
Date and
Version
of the chapter.
Updated the
section.
the Device & Pin Options dialog box in the Quartus II software uses a
32-bit CRC circuit to ensure data reliability and is one of the best options
for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry
in Stratix II devices, eliminating the need for external logic. For Stratix II
devices, CRC is computed by the device during configuration and
checked against an automatically computed CRC during normal
operation. The CRC_ERROR pin reports a soft error when configuration
SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built in the Stratix II devices to perform error
detection automatically. This error detection circuitry in Stratix II devices
constantly checks for errors in the configuration SRAM cells while the
device is in user mode. You can monitor one external pin for the error and
use it to trigger a re-configuration cycle. You can select the desired time
between checks by adjusting a built-in clock divider.
Software Interface
In the Quartus II software version 4.1 and later, you can turn on the
automated error detection CRC feature in the Device & Pin Options
dialog box. This dialog box allows you to enable the feature and set the
internal frequency of the CRC between 400 kHz to 50 MHz. This controls
the rate that the CRC circuitry verifies the internal configuration SRAM
bits in the FPGA device.
For more information on CRC, refer to AN 357: Error Detection Using CRC
in Altera FPGA Devices.
Table 3–7
“Temperature Sensing Diode (TSD)”
Changes Made
shows the revision history for this chapter.
Summary of Changes
—
—
Altera Corporation
May 2007