EP2S90F1020C5N Altera, EP2S90F1020C5N Datasheet - Page 188

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EP2S90F1020C5N

Manufacturer Part Number
EP2S90F1020C5N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020C5N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1918
EP2S90F1020C5N

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0
Timing Model
5–52
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
Input delay from
pin to internal
cells
Input delay from
pin to input
register
Delay from
output register
to output pin
Output enable
pin delay
Table 5–70. Stratix II IOE Programmable Delay on Row Pins
Parameter
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the
latest version of the Quartus II software.
The first number is the minimum timing parameter for industrial devices. The second number is the minimum
timing parameter for commercial devices.
The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number
applies to -3 speed grade EP2S130 and EP2S180 devices.
Table
5–70:
Pad to I/O
dataout to logic
array
Pad to I/O input
register
I/O output
register to pad
t
Paths Affected
X Z
, t
Z X
Default Capacitive Loading of Different I/O Standards
See
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
Table 5–71. Default Loading of Different I/O Standards for Stratix II (Part 1
of 2)
Table 5–71
Available
Settings
64
8
2
2
for default capacitive loading of different I/O standards.
Offset
(ps)
Min
Timing
Minimum
0
0
0
0
0
0
0
0
I/O Standard
Offset
1,697
1,782
1,956
2,054
Max
(ps)
316
332
305
320
(2)
Offset
Min
(ps)
Grade
0
0
0
0
0
0
0
0
-3 Speed
Note (1)
Offset
2,876
3,020
3,270
3,434
Max
(3)
(ps)
525
525
507
507
Offset
Min
(ps)
0
0
0
0
-4 Speed
Grade
Capacitive Load
Offset
3,308
3,761
Max
(ps)
575
556
Altera Corporation
10
10
0
0
0
0
0
0
Offset
Min
(ps)
0
0
0
0
-5 Speed
Grade
April 2011
Offset
3,853
4,381
Unit
Max
(ps)
670
647
pF
pF
pF
pF
pF
pF
pF
pF

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