EP2S90F1020C5N Altera, EP2S90F1020C5N Datasheet - Page 204

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EP2S90F1020C5N

Manufacturer Part Number
EP2S90F1020C5N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020C5N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1918
EP2S90F1020C5N

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Timing Model
5–68
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
1.8-V HSTL Class II
PCI
PCI-X
1.2-V HSTL
Differential SSTL-2 Class I
(1),
Differential SSTL-2 Class II
(1),
Differential SSTL-18 Class I
(1),
Differential SSTL-18 Class II
(1),
1.8-V Differential HSTL
Class I (1),
1.8-V Differential HSTL
Class II (1),
1.5-V Differential HSTL
Class I (1),
1.5-V Differential HSTL
Class II (1),
HyperTransport technology
(4)
LVPECL
LVDS
LVDS
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 2 of 2)
(3)
(3)
(3)
(3)
(1)
Row clock inputs don’t support PCI, PCI-X, LVPECL, and differential HSTL and SSTL standards.
1.2-V HSTL is only supported on column I/O pins.
Differential HSTL and SSTL standards are only supported on column clock and DQS inputs.
HyperTransport technology is only supported on row I/O and row dedicated clock input pins.
These numbers apply to I/O pins and dedicated clock pins in the left and right I/O banks.
These numbers apply to dedicated clock pins in the top and bottom I/O banks.
Input I/O Standard
(1)
(5)
(6)
Table
(1)
(3)
(3)
(3)
(3)
(2)
5–77:
Column I/O Pins (MHz)
500
500
500
280
500
500
500
500
500
500
500
500
-3
-
-
-
-
500
500
500
500
500
500
500
500
500
500
500
-4
-
-
-
-
-
500
450
450
500
500
500
500
500
500
500
500
-5
-
-
-
-
-
500
520
520
-3
Row I/O Pins (MHz)
-
-
-
-
-
-
-
-
-
-
-
-
-
500
520
520
-4
-
-
-
-
-
-
-
-
-
-
-
-
-
500
420
420
-5
-
-
-
-
-
-
-
-
-
-
-
-
-
Dedicated Clock Inputs
500
500
500
280
500
500
500
500
500
500
500
500
717
450
717
450
-3
Altera Corporation
(MHz)
500
500
500
500
500
500
500
500
500
500
500
717
450
717
450
-4
-
April 2011
500
400
400
500
500
500
500
500
500
500
500
640
400
640
400
-5
-

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