EP2S90F1020C5 Altera, EP2S90F1020C5 Datasheet - Page 103

no-image

EP2S90F1020C5

Manufacturer Part Number
EP2S90F1020C5
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020C5

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1465
EP2S90F1020C5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S90F1020C5
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S90F1020C5
Manufacturer:
ALTERA
0
Part Number:
EP2S90F1020C5
Manufacturer:
ALTERA
0
Part Number:
EP2S90F1020C5
Manufacturer:
ALTERA
0
Part Number:
EP2S90F1020C5N
Manufacturer:
ALTERA
Quantity:
233
Part Number:
EP2S90F1020C5N
Manufacturer:
ALTERA
Quantity:
530
Part Number:
EP2S90F1020C5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S90F1020C5N
0
Altera Corporation
May 2007
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
VCCSEL
(V
VCCSEL
(V
VCCSEL
(nCE Powered by V
Stratix II
Table 2–19. Board Design Recommendations for nCEO
Table 2–20. Supported TDO/TDI Voltage Combinations (Part 1 of 2)
nCE Input Buffer Power in I/O
C C I O
C C I O
Device
Input buffer is 3.3-V tolerant.
The nCEO output buffer meets V
Input buffer is 2.5-V tolerant.
The nCEO output buffer meets V
Input buffer is 1.8-V tolerant.
An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
Bank 3 = 1.5 V)
Bank 3 = 1.8 V)
Table
high
high
low
Bank 3
2–19:
Always
V
Buffer Power
C C P D
TDI Input
C C P D
(3.3V)
= 3.3V)
For JTAG chains, the TDO pin of the first device drives the TDI pin of the
second device in the chain. The V
(TCK, TMS, TDI, and TRST) is internally hardwired to GND selecting the
3.3-V/2.5-V input buffer powered by V
V
for TDI on the second device, but that may not be possible depending on
the application.
ensure proper JTAG chain operation.
V
CCIO
C C I O
v
O H
OH
of the TDO bank from the first device to match the V
v
v
= 3.3 V V
V
(MIN) = 2.0 V.
(1)
(MIN) = 2.4 V.
3.3 V
C C I O
(1),
(1),
v
(2)
(2)
=
Stratix II TDO V
Table 2–20
Stratix II nCEO V
C C I O
v
v
v
V
= 2.5 V V
v
2.5 V
(2)
C C I O
(3),
(3),
(4)
(4)
(4)
=
contains board design recommendations to
C C I O
CCIO
C C I O
Voltage Level in I/O Bank 4
CCSEL
v
Voltage Level in I/O Bank 7
V
= 1.8 V V
v
v
(3)
1.8 V
C C I O
Stratix II Device Handbook, Volume 1
v
CCPD
input on JTAG input I/O cells
(5)
(6)
=
. The ideal case is to have the
Level shifter
C C I O
required
Level shifter
required
V
= 1.5 V V
1.5 V
C C I O
v
v
Stratix II Architecture
=
CCSEL
Level shifter
C C I O
Level shifter
Level shifter
required
required
required
V
settings
1.2 V
C C I O
v
= 1.2 V
2–95
=

Related parts for EP2S90F1020C5