EP2S90F1020C5 Altera, EP2S90F1020C5 Datasheet - Page 124

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EP2S90F1020C5

Manufacturer Part Number
EP2S90F1020C5
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020C5

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1465
EP2S90F1020C5

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Configuration
3–10
Stratix II Device Handbook, Volume 1
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error status information. This dedicated remote system upgrade circuitry
avoids system downtime and is the critical component for successful
remote system upgrades.
RSC is supported in the following Stratix II configuration schemes: FPP,
AS, PS, and PPA. RSC can also be implemented in conjunction with
advanced Stratix II features such as real-time decompression of
configuration data and design security using AES for secure and efficient
field upgrades.
See the Remote System Upgrades With Stratix II & Stratix II GX Devices
chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX
Device Handbook for more information about remote configuration in
Stratix II devices.
Configuring Stratix II FPGAs with JRunner
JRunner is a software driver that configures Altera FPGAs, including
Stratix II FPGAs, through the ByteBlaster II or ByteBlasterMV cables in
JTAG mode. The programming input file supported is in Raw Binary File
(.rbf) format. JRunner also requires a Chain Description File (.cdf)
generated by the Quartus II software. JRunner is targeted for embedded
JTAG configuration. The source code is developed for the Windows NT
operating system (OS), but can be customized to run on other platforms.
For more information on the JRunner software driver, see the JRunner
Software Driver: An Embedded Solution to the JTAG Configuration White
Paper and the source files on the Altera web site (www.altera.com).
Programming Serial Configuration Devices with SRunner
A serial configuration device can be programmed in-system by an
external microprocessor using SRunner. SRunner is a software driver
developed for embedded serial configuration device programming that
can be easily customized to fit in different embedded systems. SRunner is
able to read a .rpd file (Raw Programming Data) and write to the serial
configuration devices. The serial configuration device programming time
using SRunner is comparable to the programming time when using the
Quartus II software.
For more information about SRunner, see the SRunner: An Embedded
Solution for EPCS Programming White Paper and the source code on the
Altera web site at www.altera.com.
For more information on programming serial configuration devices, see
the Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet in the
Configuration Handbook.
Altera Corporation
May 2007

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