EP2S90F1020C5 Altera, EP2S90F1020C5 Datasheet - Page 221

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EP2S90F1020C5

Manufacturer Part Number
EP2S90F1020C5
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020C5

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1465
EP2S90F1020C5

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Altera Corporation
April 2011
Notes to
(1)
(2)
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
LVPECL
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 2 of 2)
DDIO Column Output I/O
Table 5–85
The DCD specification is based on a no logic array noise condition.
Table
Standard
5–85:
assumes the input clock has zero DCD.
Notes
3.3-V LVTTL
3.3-V LVCMOS
2.5V
1.8V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 1 of 2)
Row DDIO Output I/O
(1),
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
3.3/2.5 V
(2)
Standard
335
320
330
330
330
330
420
180
TTL/CMOS
Clock Port (No PLL in the Clock Path)
1.8/1.5 V
385
385
390
360
470
180
390
375
Maximum DCD (PLL Output Clock Feeding
Note (1)
-3 Device
110
105
65
75
85
65
60
50
50
55
Stratix II Device Handbook, Volume 1
DDIO Clock Port)
SSTL-2
2.5 V
180
155
65
70
60
60
60
90
DC & Switching Characteristics
-4 & -5 Device
SSTL/HSTL
1.8/1.5 V
100
100
105
100
165
180
75
90
75
70
65
70
70
65
80
70
70
70
Unit
ps
ps
ps
ps
ps
ps
ps
ps
Unit
5–85
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps

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