EP2S90F1020C5 Altera, EP2S90F1020C5 Datasheet - Page 89

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EP2S90F1020C5

Manufacturer Part Number
EP2S90F1020C5
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020C5

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1465
EP2S90F1020C5

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0
Figure 2–55. Output TIming Diagram in DDR Mode
Altera Corporation
May 2007
EP2S15
EP2S30
EP2S60
Table 2–14. DQS & DQ Bus Mode Support (Part 1 of 2)
Device
From Internal
484-pin FineLine BGA
672-pin FineLine BGA
484-pin FineLine BGA
672-pin FineLine BGA
484-pin FineLine BGA
672-pin FineLine BGA
1,020-pin FineLine BGA
Registers
DDR output
Package
CLK
The Stratix II IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations. The negative-edge-clocked
OE register holds the OE signal inactive until the falling edge of the clock.
This is done to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Stratix II devices also have
dedicated phase-shift circuitry for interfacing with external memory
interfaces. Stratix II devices support DDR and DDR2 SDRAM, QDR II
SRAM, RLDRAM II, and SDR SDRAM memory interfaces. In every
Stratix II device, the I/O banks at the top (banks 3 and 4) and bottom
(banks 7 and 8) of the device support DQ and DQS signals with DQ bus
modes of ×4, ×8/×9, ×16/×18, or ×32/×36.
of DQ and DQS buses that are supported per device.
A1
B1
B1
A1
Number of
×4 Groups
B2
A2
B2
18
18
18
36
8
8
8
A2
A3
B3
B3
×8/×9 Groups
Number of
Note (1)
A3
18
4
8
4
8
4
8
A4
B4
B4
Stratix II Device Handbook, Volume 1
A4
×16/×18 Groups
Table 2–14
Number of
0
4
0
4
0
4
8
Stratix II Architecture
shows the number
×32/×36 Groups
Number of
0
0
0
0
0
0
4
2–81

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