IC STRATIX II FPGA 90K 780-FBGA

EP2S90F780I4N

Manufacturer Part NumberEP2S90F780I4N
DescriptionIC STRATIX II FPGA 90K 780-FBGA
ManufacturerAltera
SeriesStratix® II
EP2S90F780I4N datasheet
 


Specifications of EP2S90F780I4N

Number Of Logic Elements/cells90960Number Of Labs/clbs4548
Total Ram Bits4520488Number Of I /o534
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case780-FBGA
Family NameStratix IINumber Of Logic Blocks/elements90960
# I/os (max)534Frequency (max)711.24MHz
Process Technology90nm (CMOS)Operating Supply Voltage (typ)1.2V
Logic Cells90960Ram Bits4520488
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count780
Package TypeFC-FBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-2171
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This section provides the data sheet specifications for Stratix
This section contains feature definitions of the internal architecture,
configuration and JTAG boundary-scan testing information, DC
operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix II devices.
This section contains the following chapters:
Revision History
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Altera Corporation
Section I. Stratix II Device
Family Data Sheet
Chapter 1, Introduction
Chapter 2, Stratix II Architecture
Chapter 3, Configuration & Testing
Chapter 4, Hot Socketing & Power-On Reset
Chapter 5, DC & Switching Characteristics
Chapter 6, Reference & Ordering Information
®
II devices.
Section I–1

EP2S90F780I4N Summary of contents

  • Page 1

    ... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. Altera Corporation Section I. Stratix II Device Family Data Sheet Chapter 1, Introduction Chapter 2, Stratix II Architecture Chapter 3, Configuration & ...

  • Page 2

    ... Stratix II Device Family Data Sheet Section I–2 Stratix II Device Handbook, Volume 1 Altera Corporation ...

  • Page 3

    ... Altera Corporation May 2007 ® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper 15,600 to 179,400 equivalent LEs; see New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance ...

  • Page 4

    ... Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM Support for multiple intellectual property megafunctions from ® Altera MegaCore functions and Altera Megafunction Partners SM Program (AMPP ) megafunctions Support for design security using configuration bitstream ...

  • Page 5

    ... To ensure that a board layout supports migratable densities within one package offering, enable the applicable vertical migration path within the Quartus II software (Assignments menu > Device > Migration Devices). Altera Corporation May 2007 Tables 1–2 and 1–3). ...

  • Page 6

    ... I/O pins are migratable between the two devices. 672-Pin 780-Pin FineLine BGA FineLine BGA ( determine if your user I/O assignments are correct, run the I/O Assignment Analysis command in the Quartus II software (Processing > Start > Start I/O Assignment Analysis). 1020-Pin 1508-Pin FineLine BGA FineLine BGA Altera Corporation May 2007 ...

  • Page 7

    ... Industrial -4 EP2S30 Commercial -3, -4, -5 Industrial -4 EP2S60 Commercial -3, -4, -5 Industrial -4 EP2S90 Commercial Industrial EP2S130 Commercial Industrial EP2S180 Commercial Industrial Altera Corporation May 2007 Table 1–5 shows Stratix II device speed-grade 484-Pin 672-Pin 780-Pin Hybrid FineLine FineLine FineLine BGA BGA BGA -3, - -3, - -3, - -4, -5 -4, -5 ...

  • Page 8

    ... Updated “Features” section. February 2004, Added document to the Stratix II Device Handbook. v1.0 1–6 Stratix II Device Handbook, Volume 1 shows the revision history for this chapter. Changes Made Summary of Changes — — — — — — — — — — Altera Corporation May 2007 ...

  • Page 9

    ... DSP blocks are grouped into columns across the device and operate 450 MHz. Altera Corporation May 2007 2. Stratix II Architecture ® II devices contain a two-dimensional row- and column-based ...

  • Page 10

    ... LABs technology I/O TM IOEs Support DDR, PCI, PCI-X, SSTL-3, SSTL-2, HSTL-1, HSTL-2, LVDS, HyperTransport & other I/O Standards IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs M-RAM Block LABs LABs LABs LABs LABs LABs Altera Corporation May 2007 ...

  • Page 11

    ... LAB. Register chain connections transfer the output of an ALM register to the adjacent ALM register in an LAB. The Quartus associated logic in an LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. Altera Corporation May 2007 M4K RAM M-RAM Columns/Blocks ...

  • Page 12

    ... Variable Speed & Length Local Interconnect LAB Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows ALMs Direct link interconnect from adjacent block Direct link interconnect to adjacent block Column Interconnects of Variable Speed & Length Figure 2–3 Altera Corporation May 2007 ...

  • Page 13

    ... By default, the Quartus II software uses a NOT gate push-back technique to achieve preset. If you disable the NOT gate push-up option or assign a given register to power up high using the Quartus II software, the preset is achieved using the asynchronous load Altera Corporation May 2007 Local Figure ...

  • Page 14

    ... This adaptability allows the ALM to be 2–6 Stratix II Device Handbook, Volume 1 shows the LAB control signal generation circuit. There are two unique clock signals per LAB. labclk0 labclk1 labclk2 labclkena0 labclkena1 or asyncload or labpreset interconnect's inherent low TM labclr1 syncload labclkena2 labclr0 synclr Altera Corporation May 2007 ...

  • Page 15

    ... Figure 2–5. High-Level Block Diagram of the Stratix II ALM shared_arith_in dataf0 datae0 dataa datab Combinational Logic datac datad datae1 dataf1 shared_arith_out Altera Corporation May 2007 Figure 2–5 shows a high-level block Figure 2–6 carry_in reg_chain_in adder0 D adder1 D carry_out reg_chain_out Stratix II Device Handbook, Volume 1 ...

  • Page 16

    ... Adaptive Logic Modules Figure 2–6. Stratix II ALM Details 2–8 Stratix II Device Handbook, Volume 1 Altera Corporation May 2007 ...

  • Page 17

    ... ALM or LAB; and the register chain connection--are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset/load, synchronous clear, Altera Corporation May 2007 Figure Normal mode Extended LUT mode ...

  • Page 18

    ... Figure 2–7 2–10 Stratix II Device Handbook, Volume 1 section for more information on the LAB-wide control signals. shows the supported LUT combinations in normal mode. “LAB Control Altera Corporation May 2007 ...

  • Page 19

    ... The normal mode provides complete backward compatibility with four- input LUT architectures. Two independent functions of four inputs or less can be implemented in one Stratix II ALM. In addition, a five-input function and an independent three-input function can be implemented without sharing inputs. Altera Corporation May 2007 Note (1) dataf0 datae0 ...

  • Page 20

    ... Stratix II Device Handbook, Volume 1 Figure 2–8. The shared inputs are dataa, datab, datac, and Implementation in 1 ALM dataf0 datae0 out0 dataa datab (Function0) datac datad out1 (Function1) datae1 dataf1 Six-Input combout0 LUT Six-Input combout1 LUT Figure 2–9). If Altera Corporation May 2007 ...

  • Page 21

    ... Functions that fit into the template shown in in designs. These functions often appear in designs as “if-else” statements in Verilog HDL or VHDL code. Altera Corporation May 2007 6-Input LUT These inputs are available for register packing. ...

  • Page 22

    ... ALM in the LAB. ALMs in arithmetic mode can drive out registered and/or unregistered versions of the adder outputs. 2–14 Stratix II Device Handbook, Volume 1 combout0 D Q reg0 Figure 2–11, the carry-in signal feeds to To general or local routing To general or local routing Altera Corporation May 2007 ...

  • Page 23

    ... In this case, the data ‘Y’ drives the syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the syncload signal is de-asserted and ‘X’ drives the data port of the registers. Altera Corporation May 2007 carry_in 4-Input ...

  • Page 24

    ... Logic syncload ALM 2 X[2] Comb & X[2] Adder Y[2] Logic syncload Comb & Adder Logic R[0] To general local routing reg0 R[1] To general local routing reg1 R[2] To general local routing reg0 To local routing & carry_out then to LAB-wide syncload Altera Corporation May 2007 ...

  • Page 25

    ... This shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an adder tree. Altera Corporation May 2007 “MultiTrack Interconnect” on page 2–22 Figure 2–13 shows the ALM in shared arithmetic mode. ...

  • Page 26

    ... Stratix II Device Handbook, Volume 1 shared_arith_in carry_in 4-Input LUT D 4-Input LUT 4-Input LUT D 4-Input LUT carry_out shared_arith_out Figure 2–14. The partial sum (S[2..0]) and the To general or local routing To general or Q local routing reg0 To general or local routing To general or Q local routing reg1 Altera Corporation May 2007 ...

  • Page 27

    ... The shared arithmetic chains can begin in either the first or fifth ALM in an LAB. The Quartus II Compiler creates shared arithmetic chains longer than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long shared Altera Corporation May 2007 ALM Implementation ALM 1 ...

  • Page 28

    ... ALMs while saving local interconnect resources (see advantage of these resources to improve utilization and performance. 2–20 Stratix II Device Handbook, Volume 1 “MultiTrack Interconnect” on page 2–22 Figure 2–15). The Quartus II Compiler automatically takes section for more Altera Corporation May 2007 ...

  • Page 29

    ... Figure 2–15. Register Chain within an LAB Combinational Logic Combinational Logic Note to Figure 2–15: (1) The combinational or adder logic can be utilized to implement an unrelated, un-registered function. See the information on register chain interconnect. Altera Corporation May 2007 Note (1) reg_chain_in adder0 D adder1 D adder0 D adder1 D reg_chain_out “MultiTrack Interconnect” on page 2–22 ...

  • Page 30

    ... Stratix II Device Handbook, Volume 1 Direct link interconnects between LABs and adjacent blocks R4 interconnects traversing four blocks to the right or left R24 row interconnects for high-speed access across the length of the device technology. The MultiTrack TM Altera Corporation May 2007 ...

  • Page 31

    ... C4 and C16 interconnects can drive R4 interconnects. (2) This pattern is repeated for every LAB in the LAB row. (3) The LABs in Figure 2–16 show the 16 possible logical outputs per LAB. Altera Corporation May 2007 Notes (1), (2), (3) Adjacent LAB can C4 and C16 Drive onto Another ...

  • Page 32

    ... Shared arithmetic chain interconnects in an LAB Carry chain interconnects in an LAB and from LAB to LAB Register chain interconnects in an LAB C4 interconnects traversing a distance of four blocks in up and down direction C16 column interconnects for high-speed vertical routing through the device Figure 2–17 Altera Corporation May 2007 ...

  • Page 33

    ... IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. Altera Corporation May 2007 Local Interconnect Routing Among ALMs in the LAB Carry Chain & ...

  • Page 34

    ... LAB's C4 interconnect Note to Figure 2–18: (1) Each C4 interconnect can drive either up or down four rows. 2–26 Stratix II Device Handbook, Volume 1 Note (1) Local Interconnect C4 Interconnect Drives Local and R4 Interconnects up to Four Rows C4 Interconnect Driving Up LAB C4 Interconnect Driving Down Altera Corporation May 2007 ...

  • Page 35

    ... Shared arithmetic chain Carry chain Register chain Local interconnect Direct link interconnect R4 interconnect R24 interconnect C4 interconnect C16 interconnect ALM M512 RAM block M4K RAM block M-RAM block DSP blocks Altera Corporation May 2007 shows the Stratix II device’s routing scheme. Destination ...

  • Page 36

    ... Stratix II Device Handbook, Volume 1 Destination Table 2–3 shows the size and features of the different RAM M512 RAM Block M4K RAM Block (32 × 18 Bits) (128 × 36 Bits) 500 MHz 550 MHz M-RAM Block (4K × 144 Bits) 420 MHz ( Altera Corporation May 2007 ...

  • Page 37

    ... However, the output of the memory block does not show the effects until the next clock edge. When applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately. Altera Corporation May 2007 M512 RAM Block M4K RAM Block (32 × ...

  • Page 38

    ... Simple dual-port RAM Single-port RAM FIFO ROM Shift register Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies to both read and write operations. Figure 2–19 shows the M512 RAM block Figure 2–20 Altera Corporation May 2007 ...

  • Page 39

    ... Figure 2–19. M512 RAM Block Control Signals Dedicated Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Altera Corporation May 2007 6 outclocken inclocken inclock outclock Stratix II Device Handbook, Volume 1 Stratix II Architecture wren outclr rden 2–31 ...

  • Page 40

    ... Stratix II Device Handbook, Volume 1 dataout M512 RAM Block clocks control signals datain address 2 LAB Row Clocks True dual-port RAM Simple dual-port RAM Single-port RAM FIFO ROM Shift register R4 Interconnect Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB Altera Corporation May 2007 ...

  • Page 41

    ... Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Altera Corporation May 2007 Figure 2–21. 6 clock_b clocken_b clock_a clocken_a Stratix II Architecture Figure 2–22 shows the M4K renwe_b aclr_b renwe_a aclr_a Stratix II Device Handbook, Volume 1 ...

  • Page 42

    ... Stratix II Device Handbook, Volume 1 36 dataout M4K RAM Block datain byte control enable signals clocks address LAB Row Clocks True dual-port RAM Simple dual-port RAM Single-port RAM FIFO R4 Interconnect Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB 6 Altera Corporation May 2007 ...

  • Page 43

    ... LABs and another 16 possible from the right adjacent LAB. M-RAM block outputs can also connect to left and right LABs through direct link interconnect. for the EP2S130 device and the location of the M-RAM interfaces. Figures 2–25 the logic array. Altera Corporation May 2007 Figure clocken_a renwe_a aclr_b ...

  • Page 44

    ... Blocks Blocks Note to Figure 2–24: (1) The device shown is an EP2S130 device. The number and position of M-RAM blocks varies in other devices. 2–36 Stratix II Device Handbook, Volume 1 Note (1) M-RAM Block M-RAM Block M-RAM Block DSP LABs Blocks DSP Blocks Altera Corporation May 2007 ...

  • Page 45

    ... Blocks LABs in Row M-RAM Boundary Note to Figure 2–25: (1) Only R24 and C16 interconnects cross the M-RAM block boundaries. Altera Corporation May 2007 Note (1) Row Unit Interface Allows LAB Rows to Drive Port B Datain, Dataout, Address and Control Signals to and from M-RAM Block R0 ...

  • Page 46

    ... Stratix II Device Handbook, Volume 1 C4 Interconnect R4 and R24 Interconnects Row Interface Block M-RAM Block to LAB Row Interface Block Interconnect Region shows the input and output data signal connections along with M-RAM Block dataout_a[ ] datain_a[ ] addressa[ ] addr_ena_a renwe_a byteena clocken_a clock_a aclr_a Altera Corporation May 2007 ...

  • Page 47

    ... Table 2–4. M-RAM Row Interface Unit Signals Unit Interface Block f See the TriMatrix Embedded Memory Blocks in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook for more information on TriMatrix memory. Altera Corporation May 2007 Input Signals L0 datain_a[14..0] byteena_a[1..0] L1 datain_a[29 ...

  • Page 48

    ... Each DSP block can be configured to support up to: Eight 9 × 9-bit multipliers Four 18 × 18-bit multipliers One 36 × 36-bit multiplier This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger multiplication functions. Altera Corporation May 2007 ...

  • Page 49

    ... Figure 2–27 Figure 2–27. DSP Blocks Arranged in Columns Altera Corporation May 2007 shows one of the columns with surrounding LAB rows. DSP Block Column DSP Block 4 LAB Rows Stratix II Device Handbook, Volume 1 Stratix II Architecture 2–41 ...

  • Page 50

    ... Each device has either the numbers of 9 × 9-, 18 × 18 × 36-bit multipliers shown. The total number of multipliers for each device is not the sum of all the multipliers. shows the top-level diagram of the DSP block configured for Note (1) Total 18 × 18 Total 36 × 36 Multipliers Multipliers 144 36 192 48 252 63 384 96 Altera Corporation May 2007 ...

  • Page 51

    ... Optional Serial Shift Register Outputs to PRN Next DSP Block the Column Optional Input Register ENA Stage with Parallel Input or CLRN Shift Register Configuration Altera Corporation May 2007 Adder Output Block Multiplier Block PRN D Q Q1.15 Optional Stage Configurable Round/ as Accumulator or Dynamic Saturate ...

  • Page 52

    ... DSP 9 × × 18 Four multipliers with four product outputs - Two 52-bit multiply- accumulate blocks Two two-multiplier adder (one 18 × 18 complex multiply) One four-multiplier adder 36 × 36 One multiplier with one product output - - - Altera Corporation May 2007 ...

  • Page 53

    ... LAB though direct link interconnects. All 36 outputs can drive to R4 and C4 routing interconnects. Outputs can drive right- or left-column routing. Figures 2–29 Figure 2–29. DSP Block Interconnect Interface Altera Corporation May 2007 and 2–30 show the DSP block interfaces to LAB rows. ...

  • Page 54

    ... Stratix II Device Handbook, Volume 1 R4 Interconnect DSP Block Row Structure 16 12 Control 36 A[17..0] OA[17..0] B[17..0] OB[17..0] Row Interface Block 36 Inputs per Row Direct Link Outputs Direct Link Interconnect to Adjacent LABs from Adjacent LAB 36 LAB 36 36 Outputs per Row Altera Corporation May 2007 ...

  • Page 55

    ... Table 2–7. DSP Block Signal Sources & Destinations LAB Row at Interface f See the DSP Blocks in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook, for more information on DSP blocks. Altera Corporation May 2007 Table 2–7. Control Signals Generated 0 clock0 ...

  • Page 56

    ... Global Clocks CLK pins, PLL outputs, or internal logic v Table 2–8: Dynamic source clock selection is supported for selecting between CLKp pins and PLL outputs only. shows global and regional clock Regional Clocks CLK pins, PLL outputs, or internal logic ( Altera Corporation May 2007 ...

  • Page 57

    ... PLL outputs internal logic. The regional clock networks provide the lowest clock delay and skew for logic contained in a single quadrant. The CLK clock pins symmetrically drive the RCLK networks in a particular quadrant, as shown in Altera Corporation May 2007 Figure 2–31 shows the 16 dedicated CLK CLK[15 ...

  • Page 58

    ... Stratix II Device Handbook, Volume 1 RCLK[31..28] RCLK[27..24] CLK[15..12] CLK[7..4] Regional Clocks Only Drive a Device Quadrant from Specified CLK Pins, PLLs or Core Logic within that Quadrant RCLK[11..8] RCLK[15..12] 2–33. Corner PLLs cannot drive dual-regional clocks. RCLK[23..20] CLK[11..8] RCLK[19..16] Altera Corporation May 2007 ...

  • Page 59

    ... LAB level to select three of the six row clocks to feed the ALM registers in the LAB (see Figure 2–34). Figure 2–34. Hierarchical Clock Networks Per Quadrant Global Clock Network [15..0] Regional Clock Network [7..0] Altera Corporation May 2007 Clock Pins or PLL Clock Outputs Can Drive Dual-Regional Network CLK[11 ...

  • Page 60

    ... IO_CLKG[7:0] the Quadrant 8 2–52 Stratix II Device Handbook, Volume 1 and 2–36 show the quadrant relationship to the I/O clock IO_CLKA[7:0] IO_CLKB[7: Clocks in 24 Clocks in the Quadrant 24 Clocks in 24 Clocks in the Quadrant 8 IO_CLKF[7:0] IO_CLKE[7:0] 8 I/O Clock Regions IO_CLKC[7:0] 8 IO_CLKD[7:0] 8 Altera Corporation May 2007 ...

  • Page 61

    ... Quartus II software automatically selects the clocking resources if not specified. Clock Control Block Each global clock, regional clock, and PLL external clock output has its own clock control block. The control block has two functions: ■ ■ Altera Corporation May 2007 IO_CLKB[7:0] IO_CLKC[7:0] IO_CLKD[7: ...

  • Page 62

    ... A glitch or runt pulse has a width that is less than the width of the highest frequency input clock signal. To prevent logic errors within the FPGA, Altera recommends that you build circuits that filter out glitches and runt pulses. through 2– ...

  • Page 63

    ... Figure 2–38. Regional Clock Control Blocks Notes to (1) (2) (3) Altera Corporation May 2007 CLKp Pin PLL Counter 2 Outputs (3) Enable/ Disable RCLK Figure 2–38: These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode operation. ...

  • Page 64

    ... The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block. Static Clock Select (1) Internal Logic Static Clock Select (1) Altera Corporation May 2007 ...

  • Page 65

    ... I/O support. Enhanced and fast PLLs work together with the Stratix II high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth. Altera Corporation May 2007 The following restrictions for the input clock pins apply: • ...

  • Page 66

    ... EP2S130 devices in the 1020-pin and 1508-pin packages contain 12PLLs. The EP2S130 device in the 780-pin package contains fast PLLs 1–4 and enhanced PLLs 5 and 6. 2–58 Stratix II Device Handbook, Volume 1 Table 2–9 Fast PLLs shows the PLLs available for Enhanced PLLs Altera Corporation May 2007 ...

  • Page 67

    ... If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin. (8) Every Stratix II device has at least two enhanced PLLs with one single-ended or differential external feedback input per PLL. Altera Corporation May 2007 shows the enhanced PLL and fast PLL features in Stratix II Enhanced PLL (1) m/(n × ...

  • Page 68

    ... Figures 2–41 fast PLL outputs and the side clock pins. 2–60 Stratix II Device Handbook, Volume 1 shows a top-level diagram of the Stratix II device and PLL CLK[15..12 CLK[7..4] and 2–42 shows the global and regional clocking from the 10 FPLL10CLK 4 CLK[8..11 FPLL9CLK Altera Corporation May 2007 ...

  • Page 69

    ... Figure 2–41. Global & Regional Clock Connections from Center Clock Pins & Fast PLL Outputs Notes to (1) (2) Altera Corporation May 2007 Note (1) Figure 2–41: EP2S15 and EP2S30 devices only have four fast PLLs ( and 4), but the connectivity from these four PLLs to the global and regional clock networks remains the same as shown ...

  • Page 70

    ... The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL. Altera Corporation May 2007 ...

  • Page 71

    ... CLK pins. The connections to the global and regional clocks from the top clock pins and enhanced PLL outputs is shown in pins is shown in Altera Corporation May 2007 shows the global and regional clocking from enhanced PLL Table 2–11. The connections to the clocks from the bottom clock Table 2– ...

  • Page 72

    ... PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL. 2–64 Stratix II Device Handbook, Volume 1 PLL 11 PLL PLL 12 PLL 6 RCLK31 RCLK30 RCLK29 RCLK28 G15 G14 G13 G12 RCLK12 RCLK13 RCLK14 RCLK15 Altera Corporation May 2007 ...

  • Page 73

    ... Top Side Global & Regional Clock Network Connectivity Clock pins v CLK12p v CLK13p v CLK14p v CLK15p CLK12n CLK13n CLK14n CLK15n Drivers from internal logic GCLKDRV0 GCLKDRV1 GCLKDRV2 GCLKDRV3 RCLKDRV0 RCLKDRV1 RCLKDRV2 RCLKDRV3 RCLKDRV4 RCLKDRV5 RCLKDRV6 RCLKDRV7 Enhanced PLL 5 outputs Altera Corporation May 2007 Stratix II Device Handbook, Volume 1 ...

  • Page 74

    ... Table 2–12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL Outputs (Part Bottom Side Global & Regional Clock Network Connectivity Clock pins v CLK4p v CLK5p v CLK6p v CLK7p CLK4n CLK5n CLK6n CLK7n Drivers from internal logic GCLKDRV0 GCLKDRV1 GCLKDRV2 2–66 Stratix II Device Handbook, Volume (Part Altera Corporation May 2007 ...

  • Page 75

    ... Table 2–12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL Outputs (Part Bottom Side Global & Regional Clock Network Connectivity GCLKDRV3 RCLKDRV0 RCLKDRV1 RCLKDRV2 RCLKDRV3 RCLKDRV4 RCLKDRV5 RCLKDRV6 RCLKDRV7 Enhanced PLL 6 outputs Enhanced PLL 12 outputs Altera Corporation May 2007 Stratix II Device Handbook, Volume 1 Stratix II Architecture v v ...

  • Page 76

    ... Phase Frequency Spectrum Detector 8 Charge Loop PFD VCO Pump Filter /m Lock Detect & Filter VCO Phase Selection Affecting All Outputs From Adjacent PLL Post-Scale Counters /c0 /c1 4 Global Clocks / Regional Clocks /c3 6 I/O Buffers (3) /c4 /c5 to I/O or general routing Altera Corporation May 2007 ...

  • Page 77

    ... I/O support. I/O Structure The Stratix II IOEs provide many features, including: ■ ■ ■ ■ ■ ■ ■ ■ Altera Corporation May 2007 Figure 2–45 shows a diagram of the fast PLL. Notes (1), (2), (3) VCO Phase Selection Selectable at each PLL Output Port Phase ...

  • Page 78

    ... Stratix II Device Handbook, Volume 1 Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Programmable input and output delays Open-drain outputs DQ and DQS I/O pins Double data rate (DDR) registers Figure 2–46 shows the Stratix II IOE structure. The Altera Corporation May 2007 ...

  • Page 79

    ... There are up to four IOEs per row I/O block and four IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 2–47 Figure 2–48 Altera Corporation May 2007 OE Register D Q ...

  • Page 80

    ... Stratix II Device Handbook, Volume 1 Note (1) C4 Interconnect I/O Block Local Interconnect 32 io_dataina[3..0] io_datainb[3..0] Direct Link Interconnect to Adjacent LAB io_clk[7:0] 32 Data & Control Signals from Logic Array (1) Horizontal I/O Block Horizontal I/O Block Contains up to Four IOEs Altera Corporation May 2007 ...

  • Page 81

    ... Altera Corporation May 2007 Note (1) Vertical I/O Block ...

  • Page 82

    ... Stratix II Device Handbook, Volume 1 “PLLs & Clock Networks” illustrates the signal paths through the I/O block. To Other IOEs oe ce_in ce_out Control aclr/apreset Signal Selection sclr/spreset clk_in clk_out Figure 2–50 illustrates the control signal section). IOE Altera Corporation May 2007 ...

  • Page 83

    ... The OE register can be used for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from local interconnect in the associated LAB, dedicated I/O clocks, and the column and row interconnects. Altera Corporation May 2007 ce_out clk_out ...

  • Page 84

    ... Pin Delay Drive Strength Control ENA Open-Drain Output CLRN/PRN Input Pin to Logic Array Delay Input Pin to Input Register Delay Input Register D Q ENA CLRN/PRN t Delay CO V CCIO PCI Clamp (2) V CCIO Programmable Pull-Up Resistor On-Chip Termination Bus-Hold Circuit Altera Corporation May 2007 ...

  • Page 85

    ... Stratix II devices have six registers in the IOE, which support DDR interfacing by clocking data on both positive and negative clock edges. The IOEs in Stratix II devices support DDR inputs, DDR outputs, and bidirectional DDR modes. Altera Corporation May 2007 Table 2–13 shows the programmable delays for Stratix II ...

  • Page 86

    ... DDR input timing Notes (1), (2), (3) VCCIO To DQS Logic Block (3) I nput Pin to Input RegisterDelay Input Register D Q ENA CLRN/PRN Latch Input Register ENA ENA CLRN/PRN CLRN/PRN shows an IOE PCI Clamp (4) VCCIO Programmable Pull-Up Resistor On-Chip Termination Bus-Hold Circuit Altera Corporation May 2007 ...

  • Page 87

    ... These output registers are multiplexed by the clock to drive the output pin at a ×2 rate. One output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time. Figure 2–55 Altera Corporation May 2007 ...

  • Page 88

    ... Used for DDR, DDR2 ENA CLRN/PRN SDRAM Output Register D Q Output Pin Delay clk ENA CLRN/PRN Drive Strength Control Open-Drain Output Output Register D Q ENA CLRN/PRN PCI Clamp (3) V CCIO Programmable Pull-Up Resistor On-Chip Termination Bus-Hold Circuit Altera Corporation May 2007 ...

  • Page 89

    ... DQ and DQS buses that are supported per device. Table 2–14. DQS & DQ Bus Mode Support (Part Device Package EP2S15 484-pin FineLine BGA 672-pin FineLine BGA EP2S30 484-pin FineLine BGA 672-pin FineLine BGA EP2S60 484-pin FineLine BGA 672-pin FineLine BGA 1,020-pin FineLine BGA Altera Corporation May 2007 ...

  • Page 90

    ... DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device. 2–82 Stratix II Device Handbook, Volume 1 Note (1) Number of Number of ×4 Groups ×8/×9 Groups ×16/×18 Groups illustrates the phase-shift reference circuit control of each Number of Number of ×32/×36 Groups Altera Corporation May 2007 ...

  • Page 91

    ... I/O performance. For all I/O standards, the minimum setting is the lowest drive strength that guarantees the I minimum settings provides signal slew rate control to reduce system noise and signal overshoot. Altera Corporation May 2007 Notes (1), (2), (3), (4) From PLL 5 (3) CLK[15 ...

  • Page 92

    ... Table 2–15: The Quartus II software default current setting is the maximum setting for each I/O standard. Note ( Current Strength OH OL Setting (mA) for Row I/O Pins 12, 10 Altera Corporation May 2007 ...

  • Page 93

    ... Altera Corporation May 2007 level of the output pin’s bank. 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL (on input and output clocks only) HyperTransport technology Differential 1 ...

  • Page 94

    ... Output Supply Board Termination Voltage (V ) (V) Voltage (V ) (V) CCIO TT 3.3 - 3.3 - 2.5 - 1.8 - 1.5 - 3.3 - 3.3 - 2.5 (3) - 3.3 - 2.5 - 1.5 0.75 1.8 0.90 1.8 0.90 2.5 1.25 1.2 0.6 1.5 0.75 1.8 0.9 1.8 0.90 Altera Corporation May 2007 ...

  • Page 95

    ... SSTL-18 Class II and HSTL outputs. The top and bottom I/O banks support all single-ended I/O standards. Additionally, enhanced PLL external clock output banks allow clock output capabilities such as differential support for SSTL and HSTL. Altera Corporation May 2007 Input Reference Type ...

  • Page 96

    ... LVPECL standards for input clock operations. Differential HSTL and differential SSTL standards are supported for both input and output operations. Bank 7 PLL9 VREF3B7 VREF2B7 VREF1B7 VREF0B7 DQS3B DQS2B DQS1B DQS0B groups. Refer to the REF group REF Altera Corporation May 2007 ...

  • Page 97

    ... Stratix II devices provide four types of termination: ■ ■ ■ ■ Altera Corporation May 2007 level independently. Each bank also has dedicated VREF pins bank can support LVTTL, LVCMOS, and CCIO Differential termination (R ...

  • Page 98

    ... LVTTL 3.3-V LVCMOS 2.5-V LVTTL 2.5-V LVCMOS 1.8-V LVTTL 1.8-V LVCMOS 1.5-V LVTTL 1.5-V LVCMOS SSTL-2 Class I and II SSTL-18 Class I SSTL-18 Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 1.5-V HSTL Class I 1.2-V HSTL Left & Right Banks Altera Corporation May 2007 ...

  • Page 99

    ... Clock pins CLK1, CLK3, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential on-chip termination. Clock pins CLK0, CLK2, CLK8, and CLK10 do support differential on-chip termination. Clock pins in the top and bottom banks (CLK[4..7, 12..15]) do not support differential on-chip termination. Altera Corporation May 2007 I/O Standard Support Top & ...

  • Page 100

    ... Stratix II devices, refer to the Selectable I/O Standards in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook. 2–92 Stratix II Device Handbook, Volume 1 Table 2–17 shows the list of output standards that values Altera Corporation May 2007 ...

  • Page 101

    ... These power pins are used to supply the pre-driver power to the output buffers, which increases the performance of the output pins. The VCCPD pins also power configuration input pins and JTAG input pins. Altera Corporation May 2007 On-chip parallel termination with calibration is only supported for input pins ...

  • Page 102

    ... The ideal case is to have the V Table 2–19 contains board design recommendations to Output Signal (V) 1.5 1.8 2 (3) ( (3) (3) ( maximum and V minimum value. CCIO of the bank that they reside CCIO . When CCIO of the nCEO bank in a master CCIO Altera Corporation May 2007 5.0 v ...

  • Page 103

    ... TDI on the second device, but that may not be possible depending on the application. ensure proper JTAG chain operation. Table 2–20. Supported TDO/TDI Voltage Combinations (Part TDI Input Device Buffer Power Stratix II Always V (3.3V Altera Corporation May 2007 Stratix II nCEO V Voltage Level in I/O Bank 7 CCIO 3 ...

  • Page 104

    ... HyperTransport technology through 2–26 show the number of channels that each fast PLL = Level shifter Level shifter (3) required required (3) Level shifter Level shifter required required v Level shifter Level shifter required required v v (6) Tables 2–21 through 2–26 Altera Corporation May 2007 the ...

  • Page 105

    ... FineLine BGA Transmitter Receiver 672-pin FineLine BGA Transmitter Receiver Table 2–22. EP2S30 Device Differential Channels Transmitter/ Package Receiver 484-pin FineLine BGA Transmitter Receiver 672-pin FineLine BGA Transmitter Receiver Altera Corporation May 2007 Note (1) Center Fast PLLs Total Channels PLL 1 PLL ...

  • Page 106

    ... Receiver 118 2–98 Stratix II Device Handbook, Volume 1 Note (1) Center Fast PLLs PLL 1 PLL 2 PLL Note (1) Center Fast PLLs PLL 1 PLL 2 PLL Corner Fast PLLs (4) PLL 4 PLL 7 PLL 8 PLL 9 PLL Corner Fast PLLs (4) PLL 4 PLL 7 PLL 8 PLL 9 PLL Altera Corporation May 2007 ...

  • Page 107

    ... The channels accessible by the center fast PLL overlap with the channels accessible by the corner fast PLL. Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs and 4 with the number of channels accessible by PLLs and 10. Altera Corporation May 2007 Note (1) ...

  • Page 108

    ... DPA block or bypassing the block via a control signal from the logic array. Stratix II receiver channel. 2–100 Stratix II Device Handbook, Volume 1 Figure 2– diffioclk load_en Figure 2–59 shows the block diagram + Gbps – Dedicated Transmitter Interface Regional or global clock shows the block diagram of the Altera Corporation May 2007 ...

  • Page 109

    ... SERDES circuitry. Since every channel utilizing the DPA block can have a different phase selected to sample the data, the synchronizer is needed to synchronize the data to the high-speed clock domain of the data realignment and the SERDES circuitry. Altera Corporation May 2007 D Q Data Realignment ...

  • Page 110

    ... Stratix II Device Handbook, Volume 1 Figure 2–60 DPA Clock Quadrant Quadrant Quadrant Quadrant DPA Clock shows the fast PLL and Figure 2–61 shows the Note (1) 4 LVDS Clock 4 2 Fast PLL 4 Fast PLL 3 2 LVDS Clock 4 Altera Corporation May 2007 ...

  • Page 111

    ... Clock Clock 4 2 Fast PLL 8 Note to Figure 2–61: (1) See Tables 2–22 through 2–26 for the number of channels each device supports. Altera Corporation May 2007 DPA Quadrant Quadrant Clock DPA Quadrant Quadrant Clock Stratix II Device Handbook, Volume 1 Stratix II Architecture Note (1) Fast PLL 10 ...

  • Page 112

    ... Control Block” section. Table 2–18. Summary of Changes — — — — — — — ● Added parallel on- chip termination description and specification. ● Changed RCLK names to match the Quartus II software in Table 2–13. — — — — Altera Corporation May 2007 ...

  • Page 113

    ... In “Dedicated Circuitry with DPA Support” section, removed XSBI and changed RapidIO to Parallel RapidIO. February 2004, Added document to the Stratix II Device Handbook. v1.0 Altera Corporation May 2007 Changes Made Stratix II Device Handbook, Volume 1 Stratix II Architecture Summary of Changes — — ...

  • Page 114

    ... Document Revision History 2–106 Stratix II Device Handbook, Volume 1 Altera Corporation May 2007 ...

  • Page 115

    ... The Stratix II device instruction register length is 10 bits and the USERCODE register length is 32 bits. boundary-scan register length and device IDCODE information for Stratix II devices. Altera Corporation May 2007 3. Configuration & Testing ® II devices provide Joint Test Action Group (JTAG) CCIO ® ...

  • Page 116

    ... Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. (2) For more information on using the CONFIG_IO instruction, see the MorphIO: An I/O Reconfiguration Solution for Altera Devices White Paper. 3–2 Stratix II Device Handbook, Volume 1 Description Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins ...

  • Page 117

    ... EP2S130 0000 EP2S180 0000 Notes to Table 3–3: (1) The most significant bit (MSB the left. (2) The IDCODE's least significant bit (LSB) is always 1. 1 Altera Corporation May 2007 Device EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180 IDCODE (32 Bits) Manufacturer Identity (11 Part Number (16 Bits) 0010 0000 1001 0001 ...

  • Page 118

    ... Stratix II devices are configured at system power-up with data stored in an Altera configuration device or provided by an external controller (e.g., a MAX using the fast passive parallel (FPP), active serial (AS), passive serial (PS), passive parallel asynchronous (PPA), and JTAG configuration schemes. The Stratix II device’ ...

  • Page 119

    ... The VCCSEL pin allows the V configuration inputs reside independent of the voltage required by the configuration inputs. Therefore, when selecting the Altera Corporation May 2007 , the POR time is 12 ms. setting (of the banks where the CCIO levels driven to the configuration inputs do not have concern. ...

  • Page 120

    ... V CCINT ® II/microprocessor. (Table 3–4) have a while the 1.8-V/1.5-V input CCPD, shows the pins affected by VCCSEL. VCCSEL = HIGH (connected CCPD 1.8/1.5-V input buffer is selected. Input buffer is powered the I bank. or ground. CCPD of the I/O CCIO Altera Corporation May 2007 ...

  • Page 121

    ... Serial configuration device PS MAX II device or microprocessor and flash device Enhanced configuration device Download cable (4) Altera Corporation May 2007 Table 3–5), chosen on the basis of the target Configuration data decompression to reduce configuration file storage Design security using configuration data encryption to protect your designs ...

  • Page 122

    ... Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported. (4) The supported download cables include the Altera USB Blaster universal serial bus (USB) port download cable, MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the ByteBlasterMV parallel port download cable. ...

  • Page 123

    ... FPGA that has neither the design security, nor decompression feature enabled. For more information about this feature, refer to AN 341: Using the Design Security Feature in Stratix II Devices. Contact your local Altera sales representative to request this document. Stratix II Device Handbook, Volume 1 Configuration & Testing ® ...

  • Page 124

    ... For more information on the JRunner software driver, see the JRunner Software Driver: An Embedded Solution to the JTAG Configuration White Paper and the source files on the Altera web site (www.altera.com). Programming Serial Configuration Devices with SRunner A serial configuration device can be programmed in-system by an external microprocessor using SRunner ...

  • Page 125

    ... For more information on the MicroBlaster software driver, see the Configuring the MicroBlaster Fast Passive Parallel Software Driver White Paper or the Configuring the MicroBlaster Passive Serial Software Driver White Paper on the Altera web site (www.altera.com). PLL Reconfiguration ...

  • Page 126

    ... VBN Series resistance 3–12 Stratix II Device Handbook, Volume 1 Stratix II Device tempdiodep tempdioden shows the specifications for bias voltage and current of the Parameter Minimum 80 8 0.3 Temperature-Sensing Device Typical Maximum Unit μA 100 120 μ 0.9 V 0.7 V Ω 3 Altera Corporation May 2007 ...

  • Page 127

    ... TSD. Switching I/O near the TSD pins can affect the temperature reading. Altera recommends you take temperature readings during periods of no activity in the device (for example, standby mode where no clocks are toggling in the device), such as when the nearby I/Os are state, and disable clock networks in the device ...

  • Page 128

    ... CRC between 400 kHz to 50 MHz. This controls the rate that the CRC circuitry verifies the internal configuration SRAM bits in the FPGA device. For more information on CRC, refer to AN 357: Error Detection Using CRC in Altera FPGA Devices. Document Table 3–7 Revision History Table 3– ...

  • Page 129

    ... Detection” section. ● Updated “Device Security Using Configuration Bitstream Encryption” section. ● Updated Figure 3–2. February 2004, Added document to the Stratix II Device Handbook. v1.0 Altera Corporation May 2007 Changes Made Configuration & Testing Summary of Changes — — — — ...

  • Page 130

    ... Document Revision History 3–16 Stratix II Device Handbook, Volume 1 Altera Corporation May 2007 ...

  • Page 131

    ... Hot-Socketing requirements. The hot socketing feature in Stratix II devices allows: Specifications ■ ■ ■ Altera Corporation May 2007 ® II devices offer hot socketing, which is also known as hot plug-in Board or device insertion and removal without external components or board manipulation Support for any power-up sequence Non-intrusive I/O buffers to system buses during hot insertion is within operating range ...

  • Page 132

    ... The hot socketing DC specification is The hot socketing AC specification is less and order CCIO CCINT CCPD , Power CCINT CCPD , pins CCIO CCINT CCPD , V , and V CCIO CCINT CCPD supplies must power down CC | < 300 μA. IOPIN | < for IOPIN Altera Corporation May 2007 ...

  • Page 133

    ... For more information, refer to the Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices white paper. A possible concern regarding hot-socketing is the potential for latch-up. Latch-up can occur when electrical subsystems are hot-socketed into an active system ...

  • Page 134

    ... Power On Reset Monitor Output Enable Voltage Hot Socket Tolerance Control Output Pre-Driver Input Buffer to Logic Array are powered, and it prevents CCPD CCIO or if the I/O pad voltage is higher or V CCINT leakage current charges the 3.3-V PAD Altera Corporation May 2007 , CCIO ...

  • Page 135

    ... When power is applied to a Stratix II device, a power-on-reset event occurs if V period of time (specified as a maximum dedicated input pin (PORSEL) to select POR delay times 100 ms during power-up. When the PORSEL pin is connected to ground, the POR time is 100 ms. When the PORSEL pin is connected ms. Altera Corporation May 2007 V PAD ( CCIO ...

  • Page 136

    ... Added tables. February 2004, Added document to the Stratix II Device Handbook. v1.0 4–6 Stratix II Device Handbook, Volume 1 shows the revision history for this chapter. Changes Made Summary of Changes — ● Updated hot socketing AC specification. — — — — — Altera Corporation May 2007 ...

  • Page 137

    ... Junction temperature J Notes to Tables 5–1 (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Conditions beyond those listed in operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. ...

  • Page 138

    ... Maximum Condition Unit Duty Cycles V = 4.0 V 100 % Note (1) Minimum Maximum Unit (3) 1.15 1.25 (6) 3.135 3.465 (3.00) (3.60) (3) 2.375 2.625 (3) 1.71 1.89 (3) 1.425 1.575 (3) 1.14 1.26 (4) 3.135 3.465 (3) 1.15 1.25 (3) 1.15 1.25 –0.5 4 CCIO Altera Corporation April 2011 ...

  • Page 139

    ... I V supply current CCINT (standby supply current CCPD0 CCPD (standby) Altera Corporation April 2011 Conditions For commercial use For industrial use For military use (7) Table 5–2 must rise monotonically from ground Stratix II Military Temperature Range Support shows the Stratix II device family DC electrical characteristics. ...

  • Page 140

    ... V). CCIO (3) Maximum values depend on the actual T Estimator (available at www.altera.com) or the Quartus II PowerPlay Power Analyzer feature for maximum values. See the section “Power Consumption” on page 5–20 (4) Pin pull-up resistance values are lower if an external source drives the pin higher than V I/O Standard Specifications Tables 5– ...

  • Page 141

    ... Normal Range of the EIA/JEDEC standard. (2) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook. Altera Corporation April 2011 DC & Switching Characteristics Conditions Minimum (2) ...

  • Page 142

    ... Minimum Maximum Unit 1.71 1.89 V 0.65 × V 2.25 V CCIO 0.35 × V –0.30 V CCIO V – 0.45 V CCIO 0.45 V Minimum Maximum Unit 1.425 1.575 V 0.65 × 0.30 V CCIO CCIO 0.35 × V –0.30 V CCIO 0.75 × CCIO 0.25 × CCIO Altera Corporation April 2011 ...

  • Page 143

    ... Figure 5–1. Receiver Input Waveforms for Differential I/O Standards Single-Ended Waveform V CM Differential Waveform V Figure 5–2. Transmitter Output Waveforms for Differential I/O Standards Single-Ended Waveform V CM Differential Waveform V Altera Corporation April 2011 & Switching Characteristics Positive Channel ( Negative Channel ( Ground p − ...

  • Page 144

    ... R 250 L = 100 Ω R 840 L 90 Typical Maximum Unit 2.500 2.625 V 350 900 mV 1,250 1,800 mV 450 mV 1.375 V Ω 100 110 Typical Maximum Unit 3.300 3.465 V 350 900 mV 1,250 1,800 mV 710 mV 1,570 mV Ω 100 110 , not V . CCINT CCIO Altera Corporation April 2011 ...

  • Page 145

    ... OCM OCM and low R Receiver differential input L resistor Table 5–14. 3.3-V PCI Specifications (Part Symbol Parameter V Output supply voltage CCIO V High-level input voltage IH Altera Corporation April 2011 Conditions Minimum 3.135 300 1.0 = 100 Ω R 525 L = 100 Ω R 1,650 L 90 Conditions Minimum 2 ...

  • Page 146

    ... V V CCIO Typical Maximum Unit 3 0.5 V CCIO 0.35 × CCIO V V 0.1 × CCIO Typical Maximum Unit 1.80 1.89 V 0.900 0.945 0.04 V REF REF V V – 0.125 V REF V V – 0.25 V REF V V – 0.475 V TT Altera Corporation April 2011 ...

  • Page 147

    ... V AC differential input voltage SWING (AC) V Input clock signal offset ISO voltage ΔV Input clock signal offset ISO voltage variation V AC differential cross point OX voltage (AC) Altera Corporation April 2011 Conditions Minimum 1.71 0.855 V – 0.04 REF V + 0.125 REF V + 0.25 REF I = –13.4 mA ...

  • Page 148

    ... V + 0.18 REF –0. 0. –16 Typical Maximum Unit 2.500 2.625 0.04 V REF REF 1.250 1.313 V 3. – 0.18 V REF 0. – 0. Typical Maximum Unit 2.500 2.625 0.04 V REF REF 1.250 1.313 0.30 V CCIO V – 0.18 V REF 0. – 0. Altera Corporation April 2011 ...

  • Page 149

    ... IH V (DC) Low-level DC input voltage IL V (AC) High-level AC input voltage IH V (AC) Low-level AC input voltage IL V High-level output voltage OH V Low-level output voltage OL Altera Corporation April 2011 Conditions Minimum 2.375 0.36 (V /2) – 0.2 CCIO 0.7 0.5 × /2) – 0.2 CCIO Conditions Minimum 1.14 0.48 × ...

  • Page 150

    ... OH CCIO ( – Typical Maximum Unit 1.500 1.575 V 0.750 0.788 V 0.750 0.788 – 0.1 V REF V V – 0.2 V REF V 0.4 V Typical Maximum Unit 1.500 1.575 V 0.750 0.788 V 0.750 0.788 – 0.1 V REF V V – 0.2 V REF V 0.4 V Altera Corporation April 2011 ...

  • Page 151

    ... Low-level output voltage OL Note to Table 5–26: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook. Altera Corporation April 2011 Conditions Minimum 1.425 0.2 0.68 0.4 ...

  • Page 152

    ... OH CCIO I = –16 mA (1) OH Conditions Minimum 1.71 0.2 0.78 0.4 0.68 Typical Maximum Unit 1.80 1.89 V 0.90 0.95 V 0.90 0. – 0.1 V REF V V – 0.2 V REF V 0.4 V Typical Maximum Unit 1. CCIO 1. 0 CCIO 0.90 V Altera Corporation April 2011 ...

  • Page 153

    ... Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part Notes ( Symbol Description 25-Ω R Internal series termination with S calibration (25-Ω setting) 3.3/2.5 Internal series termination without calibration (25-Ω setting) Altera Corporation April 2011 shows the Stratix II device family bus hold specifications. V Level CCIO 1.5 V 1.8 V Max Min Max Min Max 25 ...

  • Page 154

    ... V ± 1.8 V ± 1.8 V ± 1.8 V ± 1.5 V ± 1.5 V ± 1.5 V ± 1.2 V ± 1.2 V ± 1.2 V ± Industrial Unit Max ±10 % ±30 % ±30 % ±10 % ±30 % ±10 % ±30 % ±15 % ±10 % ±36 % ±15 % ±10 % ±50 % ±15 % Altera Corporation April 2011 ...

  • Page 155

    ... C Input capacitance on left/right clock inputs CLK11 C Input capacitance on dual-purpose clock output/feedback pins in PLL banks 9, 10, 11, and 12. Note to Table 5–32: (1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within ±0.5pF Altera Corporation April 2011 Conditions V = 3.3/2 3.3/2.5 shows the Stratix II device family pin capacitance. ...

  • Page 156

    ... For more information about PowerPlay tools, refer to the PowerPlay Early Power Estimator User Guide and the PowerPlay Early Power Estimator and PowerPlay Power Analyzer chapters in volume 3 of the Quartus II Handbook. The PowerPlay Early Power Estimator is available on the Altera web site at www.altera.com. See specifications. Timing Model ...

  • Page 157

    ... These numbers reflect the actual performance of the device under worst-case voltage and junction temperature conditions. Table 5–33. Stratix II Device Timing Model Status I/O Timing Measurement Methodology Altera characterizes timing delays at the worst-case process, minimum voltage, and maximum temperature for input register setup time (t and hold time (t to calculate t Figure 5– ...

  • Page 158

    ... Figure 5–3. Input Register Setup & Hold Timing Diagram For output timing, different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination for each I/O standard and with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the timing is specified up to the output pin of the FPGA device ...

  • Page 159

    ... Figure 5–4. Output Delay Timing Reporting Setup Modeled by Quartus II Notes to (1) (2) (3) Figures 5–5 output enable timing. Altera Corporation April 2011 Record the time MEAS Compare the results of steps 2 and 4. The increase or decrease in delay should be added to or subtracted from the I/O Standard Output Adder delays to yield the actual worst-case propagation delay (clock-to-output) of the PCB trace ...

  • Page 160

    ... Altera Corporation April 2011 ...

  • Page 161

    ... Figure 5–5. Measurement Setup for t OE Din OE Din Note to (1) Altera Corporation April 2011 Driving High to Tristate XZ Dout 100 Ω Dout t , Driving Low to Tristate XZ 100 Ω Dout Dout Figure 5– 1.12 V for this measurement. CCINT DC & Switching Characteristics Note (1) Enable Disable OE ½ ...

  • Page 162

    ... V CCIO Enable ½ V CCINT “0” ½ CCIO zl Notes (1)–(4) Measurement Point V ( 3.135 1.5675 3.135 1.5675 2.375 1.1875 1.710 0.855 1.425 0.7125 2.970 1.485 2.970 1.485 2.325 1.1625 2.325 1.1625 1.660 0.83 1.660 0.83 1.660 0.83 Altera Corporation April 2011 ...

  • Page 163

    ... V, less than 50-mV ripple on V CCPD Performance Table 5–36 performance values were obtained with the Quartus II software compilation of library of parameterized modules (LPM), or MegaCore functions for the finite impulse response (FIR) and fast Fourier transform (FFT) designs. Altera Corporation April 2011 Measurement Conditions V (V) V (V) CCIO REF 1 ...

  • Page 164

    ... MHz 538.79 489.23 421.05 MHz 232.07 209.11 181.38 MHz 476.19 434.02 373.13 MHz 476.19 434.78 373.13 MHz 515.46 469.48 401.60 MHz 515.46 469.48 401.60 MHz 499.00 469.48 401.60 MHz 453.30 413.22 354.10 MHz 453.30 413.22 354.10 MHz Altera Corporation April 2011 ...

  • Page 165

    ... Simple dual-port RAM 32K × 18 bit True dual-port RAM 32K × 18 bit Single port RAM 64K × 9 bit Simple dual-port RAM 64K × 9 bit True dual-port RAM 64K × 9 bit Altera Corporation April 2011 Note (1) Resources Used -3 TriMatrix DSP Speed ALUTs Memory ...

  • Page 166

    ... MHz 428.08 391.23 335.12 MHz 238.15 217.48 186.60 MHz 390.01 356.12 305.06 MHz 390.01 356.12 305.06 MHz 240.61 217.15 185.01 MHz 364.03 355.23 306.37 MHz 409.16 347.22 311.13 MHz 365.76 346.98 292.39 MHz 378.78 357.14 307.59 MHz Altera Corporation April 2011 ...

  • Page 167

    ... FFT engines, burst, three multipliers and five adders FFT function 8-bit, 1024-point, quadrant output, two parallel FFT engines, burst, four multipliers and two adders FFT function Altera Corporation April 2011 Note (1) Resources Used -3 TriMatrix DSP Speed ALUTs Memory Blocks ...

  • Page 168

    ... Performance - Speed Speed Speed Unit Grade Grade Grade (3) 345.66 308.54 276.31 MHz 349.04 327.33 268.24 MHz 388.34 364.56 306.84 MHz 369.66 364.96 307.88 MHz 378.07 340.13 291.29 MHz 398.08 356.53 280.74 MHz Altera Corporation April 2011 ...

  • Page 169

    ... This application uses registered multiplier input with output of the multiplier stage feeding the accumulator or subtractor within the DSP block. (8) This application uses the same clock source that is globally routed and connected to ports A and B. (9) This application uses locally routed clocks or differently sourced clocks for ports A and B. Altera Corporation April 2011 Note (1) Resources Used -3 TriMatrix ...

  • Page 170

    ... Unit Min Min Max Max (4) (3) 104 121 ps 104 172 200 ps 172 59 109 62 127 ps 62 234 273 ps 234 234 273 ps 234 703 820 ps 703 703 820 ps 703 162 435 162 507 ps 170 354 712 354 829 ps 372 Altera Corporation April 2011 ...

  • Page 171

    ... For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade devices offer the industrial temperature grade. (4) For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices. Altera Corporation April 2011 DC & Switching Characteristics -3 Speed -3 Speed ...

  • Page 172

    ... Speed Grade Unit Min Max Max ( 241 2,334 1,312 2,720 ps 2,311 1,302 2,693 ps 2,311 1,302 2,693 ps 1,667 924 1,943 ps 2,127 1,134 2,479 ps 3,312 2,100 3,859 ps 3,438 2,110 4,006 ps 5,117 2,939 5,962 ps 2,964 ps Altera Corporation April 2011 ...

  • Page 173

    ... Write address setup time before clock t Write address hold time after clock t Read address setup time before clock t Read address hold time after clock Altera Corporation April 2011 DC & Switching Characteristics -3 Speed -3 Speed Grade (1) Grade (2) Min Min Min Max Max (3) (3) ...

  • Page 174

    ... Note (1) -5 Speed Grade Grade Unit Min Max Max (4) 548 298 640 ps 2,695 2,102 3,141 ps 1,762 ps 1,762 ps 192 ps -5 Speed Grade Grade Unit Min Max Max (4) 2,575 1,462 3,000 272 272 ps Altera Corporation April 2011 ...

  • Page 175

    ... Numbers apply to unpacked memory modes, true dual-port memory modes, and simple dual-port memory modes that use locally routed or non-identical sources for the A and B port registers. Altera Corporation April 2011 DC & Switching Characteristics Note (1) ...

  • Page 176

    ... Note (1) -5 Speed Grade Grade Unit Min Max Max (4) 3,189 1,777 3,716 ps 1,866 192 325 ps 789 ps 322 325 ps 789 ps 322 ps 821 480 957 ps 3,332 1,950 3,884 ps 1,675 ps Altera Corporation April 2011 ...

  • Page 177

    ... For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices. Stratix II Clock Timing Parameters See Table 5–43. Stratix II Clock Timing Parameters Altera Corporation April 2011 -3 Speed -3 Speed Grade (2) Grade (3) Min Min Max Max (4) ...

  • Page 178

    ... Speed -5 Speed Unit Grade Grade 2.848 3.309 ns 2.570 2.985 ns 0.373 0.424 ns 0.095 0 Speed -5 Speed Unit Grade Grade 3.273 ns 2.949 ns 0.414 ns 0. Speed -5 Speed Unit Grade Grade 2.454 2.848 ns 2.450 2.843 ns -0.021 -0.037 ns -0.025 -0.042 ns Altera Corporation April 2011 ...

  • Page 179

    ... Table 5–49. EP2S30 Column Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial t 1.539 1.382 0.101 -0.056 Altera Corporation April 2011 -3 Speed Grade Commercial 1.262 2.113 1.267 2.109 -0.138 -0.023 -0.133 -0.027 through 5–51 show the maximum clock timing parameters -3 Speed ...

  • Page 180

    ... Grade 2.251 2.616 ns 2.247 2.611 ns –0.254 –0.302 ns –0.258 –0.307 ns -4 Speed -5 Speed Unit Grade Grade 2.567 2.990 ns 2.563 2.985 ns -0.205 -0.254 ns -0.209 -0.259 ns -4 Speed -5 Speed Unit Grade Grade 3.381 3.931 ns 3.103 3.607 ns 0.311 0.348 ns 0.033 0.024 ns Altera Corporation April 2011 ...

  • Page 181

    ... -0.148 Table 5–55. EP2S60 Row Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial t 1.439 1.444 -0.161 -0.156 Altera Corporation April 2011 -3 Speed Grade Commercial 1.739 2.920 1.574 2.678 0.057 0.278 -0.108 0.036 -3 Speed Grade Commercial 1.532 2.591 1.537 2.587 -0.167 -0 ...

  • Page 182

    ... Speed -5 Speed Unit Grade Grade 3.473 4.040 ns 3.195 3.716 ns 0.129 0.144 ns -0.149 -0. Speed -5 Speed Unit Grade Grade 3.502 4.070 ns 3.224 3.746 ns 0.119 0.134 ns -0.159 -0. Speed -5 Speed Unit Grade Grade 3.124 3.632 ns 3.120 3.627 ns -0.218 -0.264 ns -0.222 -0.269 ns Altera Corporation April 2011 ...

  • Page 183

    ... Table 5–61. EP2S130 Column Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial t 1.907 1.750 0.134 -0.023 Altera Corporation April 2011 -3 Speed Grade Commercial 1.658 2.757 1.663 2.753 -0.341 -0.193 -0.336 -0.197 through 5–63 show the maximum clock timing parameters -3 Speed ...

  • Page 184

    ... Grade 3.351 3.892 ns 3.347 3.887 ns -0.138 -0.168 ns -0.142 -0.173 ns -4 Speed -5 Speed Unit Grade Grade 3.362 3.905 ns 3.358 3.900 ns -0.089 -0.11 ns -0.093 -0.115 ns -4 Speed -5 Speed Unit Grade Grade 3.984 4.634 ns 3.706 4.310 ns 0.046 0.048 ns -0.232 -0.276 ns Altera Corporation April 2011 ...

  • Page 185

    ... -0.537 Table 5–67. EP2S180 Row Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial t 1.763 1.768 -0.542 -0.537 Altera Corporation April 2011 -3 Speed Grade Commercial 2.100 3.652 1.935 3.398 -0.29 0.053 -0.455 -0.201 -3 Speed Grade Commercial 1.844 3.273 1.849 3.269 -0.541 -0 ...

  • Page 186

    ... This is in addition to intra-clock network skew, which is modeled in the Quartus II software. 5–50 Stratix II Device Handbook, Volume 1 Table 5–68 specifies the clock skew between any Description Min Typ Max Unit ±50 ps ±100 ps ±55 ps ±110 ps ±63 ps ±125 ps ±75 ps ±150 ps Altera Corporation April 2011 ...

  • Page 187

    ... The first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices. (3) The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number applies to -3 speed grade EP2S130 and EP2S180 devices. Altera Corporation April 2011 Tables 5–69 and 5–70 for IOE programmable delay ...

  • Page 188

    ... I/O Standard -4 Speed -5 Speed (3) Grade Grade Max Min Max Min Max Offset Offset Offset Offset Offset (ps) (ps) (ps) (ps) (ps) 2,876 0 3,308 0 3,853 3,020 3,270 0 3,761 0 4,381 3,434 525 0 575 0 670 525 507 0 556 0 647 507 Capacitive Load Unit Altera Corporation April 2011 ...

  • Page 189

    ... Differential SSTL-18 Class I Differential SSTL-18 Class II 1.5-V Differential HSTL Class I 1.5-V Differential HSTL Class II 1.8-V Differential HSTL Class I 1.8-V Differential HSTL Class II LVDS HyperTransport LVPECL Altera Corporation April 2011 DC & Switching Characteristics I/O Standard Stratix II Device Handbook, Volume 1 Capacitive Load Unit 0 pF ...

  • Page 190

    ... Altera Corporation April 2011 ...

  • Page 191

    ... HSTL Class I ( 1.8-V Differential (1) HSTL Class 1.5-V Differential (1) HSTL Class 1.5-V Differential HSTL Class II ( Altera Corporation April 2011 Minimum Timing -3 Speed Grade Industrial Commercial (2) 560 587 993 294 308 557 543 569 898 277 290 462 543 569 898 277 290 ...

  • Page 192

    ... Altera Corporation April 2011 ...

  • Page 193

    ... I/O Standard Parameter Strength LVTTL ( Altera Corporation April 2011 Minimum Timing -3 Speed Grade Industrial Commercial (1) 602 631 1056 278 292 529 577 605 960 253 266 433 577 605 960 253 266 433 515 540 948 191 201 421 515 540 948 ...

  • Page 194

    ... Altera Corporation April 2011 ...

  • Page 195

    ... SSTL-2 Class ( SSTL-2 Class ( Altera Corporation April 2011 DC & Switching Characteristics Minimum Timing -3 Speed Grade Industrial Commercial (3) 1042 1093 2904 1062 1115 2970 1047 1098 2248 1067 1120 2314 974 1022 2024 994 1044 2090 976 1024 1947 996 1046 ...

  • Page 196

    ... Altera Corporation April 2011 ...

  • Page 197

    ... O P Class ( 1.2-V HSTL PCI PCI Altera Corporation April 2011 DC & Switching Characteristics Minimum Timing -3 Speed Grade Industrial Commercial (3) 877 919 1385 897 941 1451 879 921 1394 899 943 1460 879 921 1402 899 943 1468 912 956 1607 932 978 ...

  • Page 198

    ... Altera Corporation April 2011 ...

  • Page 199

    ... 1.5 Differential HSTL Class Altera Corporation April 2011 DC & Switching Characteristics Minimum Timing -3 Speed Grade Industrial Commercial (3) 912 956 1608 932 978 1674 917 962 1595 937 984 1661 896 940 1586 916 962 1652 900 944 1591 920 966 1657 ...

  • Page 200

    ... Speed Speed Speed Unit Grade Grade Grade (3) 2786 3052 3189 ps 2729 2989 3116 ps 2217 2429 2549 ps 2160 2366 2476 ps 2184 2392 2512 ps 2127 2329 2439 ps 2217 2429 2549 ps 2160 2366 2476 ps 1944 2130 2243 ps 1887 2067 2170 ps Altera Corporation April 2011 ...