EP2S90F780I4N Altera, EP2S90F780I4N Datasheet - Page 186

IC STRATIX II FPGA 90K 780-FBGA

EP2S90F780I4N

Manufacturer Part Number
EP2S90F780I4N
Description
IC STRATIX II FPGA 90K 780-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F780I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
534
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2171

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S90F780I4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S90F780I4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S90F780I4N
Manufacturer:
ALTERA
0
Timing Model
5–50
Stratix II Device Handbook, Volume 1
Note to
(1)
Clock skew adder
EP2S15, EP2S30,
EP2S60
Clock skew adder
EP2S90
Clock skew adder
EP2S130
Clock skew adder
EP2S180
Table 5–68. Clock Network Specifications
This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
Table
(1)
(1)
(1)
(1)
Name
5–68:
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks
such as global and regional clocks. Therefore, intra-clock network skew
adder is not specified.
two clock networks driving registers in the IOE.
Description
Table 5–68
specifies the clock skew between any
Min
Typ
Altera Corporation
±100
±110
±125
±150
Max
±50
±55
±63
±75
April 2011
Unit
ps
ps
ps
ps
ps
ps
ps
ps

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