EP2S90F780I4N Altera, EP2S90F780I4N Datasheet - Page 226

• Manufacturer Part Number: EP2S90F780I4N
• Description: IC STRATIX II FPGA 90K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S90F780I4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520488
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 534
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520488
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2171

High-Speed I/O Specifications
5–90
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
f
f
f
f
TCCS
SW
Output jitter
Output t
Output t
t
DPA run length
DPA jitter tolerance
DPA lock time
H S C L K
H S C L K
H S D R
H S D R D PA
DUTY
Table 5–91. High-Speed I/O Specifications for -5 Speed Grade
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
(data rate)
(clock frequency)
= f
R I S E
FA L L
Table
Symbol
H S D R
(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
5–91:
/ W
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
All differential I/O standards
All differential I/O standards
All differential I/O standards
All differential I/O standards
Data channel peak-to-peak jitter
SPI-4
Parallel Rapid I/O
Miscellaneous
Table 5–91
grade Stratix II devices.
Standard
shows the high-speed I/O timing specifications for -5 speed
Conditions
0000000000
1111111111
00001111
10010000
10101010
01010101
Training
Pattern
Transition
Density
100%
10%
25%
50%
Notes
(1),
0.44
Min
150
150
256
256
256
256
256
150
440
16
16
(4)
(4)
45
-5 Speed Grade
-
(2)
Typ
50
Altera Corporation
6,400
Max
420
500
640
840
700
500
840
200
190
290
290
55
-
Number of
repetitions
April 2011
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
Unit
ps
ps
ps
ps
ps
UI
UI
%