EP2S90F780I4N Altera, EP2S90F780I4N Datasheet - Page 72

IC STRATIX II FPGA 90K 780-FBGA

EP2S90F780I4N

Manufacturer Part Number
EP2S90F780I4N
Description
IC STRATIX II FPGA 90K 780-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F780I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
534
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2171

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S90F780I4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S90F780I4N
Manufacturer:
Altera
Quantity:
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Part Number:
EP2S90F780I4N
Manufacturer:
ALTERA
0
PLLs & Clock Networks
Figure 2–43. Global & Regional Clock Connections from Top & Bottom Clock Pins & Enhanced PLL Outputs
Notes
Notes to
(1)
(2)
(3)
2–64
Stratix II Device Handbook, Volume 1
EP2S15 and EP2S30 devices only have two enhanced PLLs (5 and 6), but the connectivity from these two PLLs to
the global and regional clock networks remains the same as shown.
If the design uses the feedback input, you lose one (or two, if FBIN is differential) external clock output pin.
The enhanced PLLs can also be driven through the global or regional clock netowrks. The global or regional clock
input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a
clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
global or regional clock. An internally generated global signal cannot drive the PLL.
(1), (2), and
Figure
2–43:
(3)
Regional
Regional
Clocks
Clocks
Clocks
Global
RCLK27
RCLK26
RCLK25
RCLK24
RCLK10
RCLK11
RCLK8
RCLK9
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 11
PLL 12
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 6
PLL 5
RCLK31
RCLK30
RCLK29
RCLK28
G15
G14
G13
G12
G4
G5
G6
G7
RCLK12
RCLK13
RCLK14
RCLK15
Altera Corporation
May 2007

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