EP2S90F780I4N Altera, EP2S90F780I4N Datasheet - Page 99
EP2S90F780I4N
Manufacturer Part Number
EP2S90F780I4N
Description
IC STRATIX II FPGA 90K 780-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S90F780I4N
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
534
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2171
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S90F780I4N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 99 of 238
- Download datasheet (3Mb)
Altera Corporation
May 2007
Note to
(1)
Series termination with
calibration
Parallel termination with
calibration
Differential termination
Table 2–17. On-Chip Termination Support by I/O Banks (Part 2 of 2)
On-Chip Termination Support
Clock pins CLK1, CLK3, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential on-chip
termination. Clock pins CLK0, CLK2, CLK8, and CLK10 do support differential on-chip termination. Clock pins in
the top and bottom banks (CLK[4..7, 12..15]) do not support differential on-chip termination.
Table
2–17:
(1)
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 Class I and II
SSTL-18 Class I and II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.2-V HSTL
SSTL-2 Class I and II
SSTL-18 Class I and II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I and II
1.2-V HSTL
LVDS
HyperTransport technology
I/O Standard Support
Top & Bottom Banks
Stratix II Device Handbook, Volume 1
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Stratix II Architecture
Left & Right Banks
v
v
2–91
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